吳凱強

Calibration-Free Post-Training Quantization with Adaptive Per-Tile MX Format Selection

資訊科學與工程研究所

模型量化、混合精度量化、模型壓縮、大語言模型、模型推理、model quantization、mixed precision quantization、model compression、large language model、inference

HachiWare: One-Shot Selective SVD in a Dual-Branch Framework for KV Cache Compression

數據科學與工程研究所

鍵值快取壓縮、長上下文推論、奇異值分解、大型語言模型、高效率推論、KV cache compression、long-context inference、singular value decomposition、large language models、efficient inference

Low-Rank Compression for Efficient Large Language Model Inference

資訊科學與工程研究所

低秩壓縮、模型壓縮、大型語言模型、高效率人工智慧、奇異值分解、Low-Rank Compression、Model Compression、Large Language Model、Efficient AI、Singular Value Decomposition

Accelerating Cell-Aware Library Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis

資訊學院碩士在職專班・共同指導：温宏斌

單元感知測試、單元內缺陷、圖論、缺陷群集、結構分析、cell-aware test、intra-cell defect、graph theory、defect clustering

Lossless and Training-Free Acceleration for Offloaded LLMs via Substitute Speculative Decoding

網路工程研究所

推測解碼、權重卸載、模型量化、模型壓縮、大語言模型、模型推理、speculative decoding、offloading、quantization、compression、large language models、inference

Integrated Model Compression and Rematerialization for Efficient On-Device Learning

網路工程研究所

邊緣學習、高效模型訓練、模型壓縮、重計算、神經結構搜索、On-device Learning、Efficient Training、Model Compression、Rematerialization、Neural Architecture Search

Memory-Efficient Split-Federated Learning Framework Considering Device and Cut-layer Heterogeneity

資訊安全研究所

拆分聯邦學習、異質性、模型逆向攻擊、低秩微調、大型語言模型、Split-Federated Learning、Heterogeneity、Model Inversion Attack、Low-rank Adaptation、Large Language Model

Wafer-View Defect-Pattern-Prominent GDBN Method Using Image-in-Image-out MetaFormer Variant

資訊科學與工程研究所

晶片測試、神經網路、百萬分之缺陷率、區域聚集性零件平均測試、VLSI testing、neural network、defective parts per million (DPPM)、geographical part average testing (GPAT)

Layer-Wise Rank Search for Low-Rank Compression of Large Language Models

資訊科學與工程研究所

大型語言模型、模型壓縮、低秩近似、奇異值分解、凸優化、Large Language Models、Model Compression、Low-Rank Approximation、Singular Value Decomposition、Convex Optimization

Machine Learning-Based IC Testing – Reliability and Security Perspectives

資訊科學與工程研究所

晶片測試、機器學習、深度學習、硬體木馬偵測、離群晶片識別、處於缺陷晶片群集中的正常晶片識別、IC testing、Machine learning、Deep learning、Hardware Trojan detection、Outlier identification、Good-die-in-bad-neighborhoods (GDBN) identification

Compressing KV-Cache in Large Language Models with Low-Rank Projection

資訊科學與工程研究所

大型語言模型、模型壓縮、鍵值快取、低秩分解、量化、Large Language Models、Model Compression、KV-Cache、Low-Rank Decomposition、Quantization

Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods

資訊科學與工程研究所

晶片測試、深度學習模型、缺陷晶片偵測、退貨授權賠償、VLSI testing、deep learning model、defective die detection、return merchandise authorization compensation

Synergizing Graph Convolutional Networks and Graph Attention Networks for Hardware Trojan Detection and Localization

資訊科學與工程研究所

硬體木馬定位、硬體安全、圖卷積神經網路、圖注意力網路、暫存器傳輸級、Hardware Trojan Localization、Hardware Security、Graph Convolutional Neural Network、Graph Attention Network、Register Transfer Level

Extensive Mapping and Routing Algorithm of NoC on Heterogeneous Architecture

資訊科學與工程研究所

片上網路、映射演算法、路由演算法、異質架構、匈牙利演算法、Network on chip、Mapping algorithm、Routing algorithm、Heterogeneous architecture、Hungarian algorithm

Predicting Suspiciousness of Target Dice using Multilayer Perceptron and Surrounding Neighbor Dice Conditions

資訊科學與工程研究所

缺陷晶片檢測、多層感知器、神經網路、晶片測試、GDBN、Multilayer Perceptron、Neural Networks、VLSI Testing

Defect-Based Test Methodologies

電子研究所・共同指導：趙家佐

自動測試圖樣產生、單元識別測試、延遲測試、瑕疵導向測試、掃描正反器、錯誤模型、Automatic test pattern generation (ATPG)、Cell-Aware Test、Delay testing、Defect-based test、Scan flip-flop、Fault modeling

Searching for Low-Rank Vision Transformer Based on Neural Architecture Search

資訊科學與工程研究所

深度學習、Vision Transformer、模型壓縮、低秩近似、神經架構搜索、Deep Learning、Model Compression、Low-Rank Approxi- mation、Neural Architecture Search

Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information

數據科學與工程研究所

晶片測試、晶圓級缺陷樣式、潛在缺陷偵測、神經網路、VLSI Testing、wafer-level defect pattern、latent defect detection、neural networks

Optimizing MultiLayer Perceptrons (MLP) based on Model Reconstruction

資訊科學與工程研究所

深度神經網路、層融合、多層感知器、邊緣裝置、Deep Neural Network、Layer Fusion、Multilayer Perceptron、Edge Device

A Fault Mitigation Methodology for AI Accelerators Based on Decomposable Systolic Arrays

資訊科學與工程研究所

錯誤減輕、人工智慧加速器、脈動陣列、fault mitigation、AI accelerator、systolic array

Robust Model Compression and Simplification for Complex MLP Models

數據科學與工程研究所

高效壓縮、硬體友善設計、低秩矩陣近似、近代多層感知器架構、efficient compression、hardware-friendly、row-rank approximation、MLP-based architectures

On the Application of Timing Speculation based on Variable-Latency Design and Approximate Computing Paradigms

資訊科學與工程研究所

時序錯誤預防、可變延遲設計、時序變動、近似計算、電壓調節、timing error prevention、variable-latency design、timing variability、approximate computing、voltage scaling

Federated-Split Learning

資訊科學與工程研究所

聯邦學習、安全多方計算、資料隱私、Federated learning、Secure multi-party computation、Data privacy

Clustering of System-level Test Failed Parts for Diagnosis

資訊科學與工程研究所

系統測試、錯誤診斷、非監督式學習、System testing、Fault diagnosis、Unsupervised learning

FOX-NAS: Fast, On-device and Explainable Neural Architecture Search

數據科學與工程研究所

神經架構搜尋、Neural architecture search

A Novel Methodology for Highly Accurate Hardware Trojan Detection

資電亥客與安全碩士學位學程

硬體特洛伊木馬、硬體特洛伊木馬偵測、支持向量機、隨機森林、路徑特徵、Hardware Trojan、Hardware Trojan Detection、Support Vector Machine、Random Forest、Path Features

Reservoir-Computing-Based Simulation System with Artificial Synaptic Devices

資訊科學與工程研究所

人工突觸、水庫計算、Reservoir Computing、Artificial Synaptic Device

Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks

數據科學與工程研究所

晶片測試、神經網路、深度學習、偵測缺陷晶片、VLSI Testing、Neural Networks、Deep Learning、Defect Die Detection

Performance and Precision Driven Configurable Systolic Array for DNN Inference Using Configurable Fusion of Multiplications

資訊科學與工程研究所

深度神經網路、近似計算、乘法累加單元、脈動陣列、Deep neural network、Approximate computing、MAC、Systolic array

ASAP: Approximate Systolic Array-based Processor for Edge AI Computation

資訊科學與工程研究所

人工智慧、脈動陣列、近似計算、時間臆測、可變動延遲設計、電壓調節、artificial intelligence、systolic array、approximate computing、timing speculation、variable latency design、voltage scaling

Cost-Effective In-Situ Sensor Deployment for On-Chip Aging Monitoring and Resilience

資訊科學與工程研究所

時間臆測、時脈借取、老化彈性、即時監測、可靠度、timing speculation、time borrowing、aging resilience、real-time monitoring

CNN-based Stochastic Regression for IDDQ Outlier Identification

資訊科學與工程研究所

異常值偵測、卷積神經網路、隨機回歸模型、空間關聯、穩態電流、outlier identification、CNN、stochastic regression、spatial correlation、iddq

Lock or Luck: Robust Logic Locking for Deep-Learning Applications Using Approximate Arithmetic

資訊科學與工程研究所

硬體安全、邏輯加密、深度學習、近似計算、hardware security、logic locking、deep-learning、approximate arithmetic

Using Path Features for Hardware Trojan Detection and Localization Based on Machine Learning Techniques

資訊科學與工程研究所

硬體木馬、硬體木馬偵測、硬體木馬定位、路徑特徵、機器學習、Hardware Trojan、Hardware Trojan Detection、Hardware Trojan Localization、Path Features、Machine Learning

On the Robustness of Power Delivery Network - A Perspective of Lifetime Reliability Trojan

資訊科學與工程研究所

硬體特洛伊、壽命型⽊⾺、電⼦飄移現象、電源供應網路、最⼩割演算法、製成變異、Hardware Trojan、Lifetime Trojan、Electromigration、Power delivery network、Min-cut algorithm、Process variation

Making Aging Useful by Recycling Aging-Induced Clock Skew

資訊科學與工程研究所

老化、可靠度、Aging、Reliability

Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs

資訊科學與工程研究所

可變動時脈設計、老化、製程變異、靜態時序分析、邏輯匝置換、Variable-Latency Design、Aging effect、Process Variation、Static Timing Analysis、Gate Sizing

Process Variation-aware Lifetime Trojan based on Power Delivery Network Tampring

資訊科學與工程研究所

硬體特洛伊、電力供應網、製程變異、壽命控制、Hardware Trojan、Power delivery network、Process Variation、Lifetime control

High-Accuracy Approximate Addition based on Carry Speculation

資訊科學與工程研究所

近似加法器、可變動延遲設計、容錯應用、Approximate adder、Variable-latency design、Error-tolerant application

Cost-Effective Transition Detector Deployment for Aging Resili-ence

資訊科學與工程研究所

剃刀正反器、訊號轉換偵測器、易錯誤路徑、訊號到達率、預測錯誤率、Razor flip-flop、Transition detector、Vulnerable path、Sensitization rate、Misprediction rate

Aging tolerance design for flip-flop-based sequential circuit

資訊科學與工程研究所

電路老化、電路可靠度、時間借取、時間偷竊、時鐘偏移、布林可滿足性問題、circuit aging、circuit reliability、time borrowing、time stealing、clock skew、Boolean satisfiability

Making Aging Useful, Intentionally by Using Duty Cycle Converters

資訊科學與工程研究所

電路老化、時鐘樹、老化時鐘偏移、工作週期轉換器、老化容忍、Aging、Clock Tree、Aging-Induced Clock Skew、Duty Cycle Converter、Aging Tolerance

Dual Timing Margins + Dual Supply Voltages: Dynamic Power Reduction Revisited for Variable-Latency Designs

資訊科學與工程研究所

可變延遲設計、時序臨界分析、基因演算法、功耗降低、Variable-latency design、Timing criticality analysis、Genetic algorithm、Power reduction

Workload-Aware Lifetime Trojan based on Statistical Aging Manipulation

資訊科學與工程研究所

硬體特洛伊、電路老化、時鐘樹、統計相關性、Hardware Trojan、Aging、Clock Tree、Correlation & Regression Analysis

Analysis and Optimization of Variable-Latency Designs in the Presence of Timing Variability

資訊科學與工程研究所

可變動延遲設計、靜態時序分析、時序變動、邏輯匝置換、粒子群體最佳化、Variable-latency design、Static timing analysis、Timing variability、Gate sizing、Particle swarm optimization

ICE-RADAR: In-situ, Cost-Effective Razor Flip-Flop Deployment for Aging Resilience

資訊科學與工程研究所

老化、即時監測、可靠度、壽命延長、aging resilience、cost-effective、Razor flip-flop、reliability、real-time monitoring