黃俊達

Quality-Aware Variable-Length LLM Compression for Deadlock-Free Parallel Decoding

電子研究所

大型語言模型、權重量化、可變長度編碼、Huffman 編碼、平行解碼、無停滯解碼、品質感知替換、large language models、weight quantization、variable-length encoding、Huffman coding、parallel decoding、stall-free decoding、quality-aware substitution

Polar Lattice Quantization for LLM Compression

電子研究所

大型語言模型、large language model

A Multi-Precision LLM Accelerator for Efficient Long-Context Inference

前瞻半導體研究所

大型語言模型加速器、長文推論、注意力機制、多精度運算、端到端推論、KV 快取量化、Microscaling 資料格式、LLM accelerator、long-context inference、attention mechanism、multi-precision computing、end-to-end inference、KV-cache quantization、Microscaling data format

Optimization of Mixture-of-Experts Models via Fine-Tuning, Quantization, and Expert Fusion

電子研究所

混合專家、大型語言模型、參數高效微調、訓練後量化、模型壓縮、專家融合、高效推論、mixture-of-experts、large language models、parameter-efficient fine-tuning、post training quantization、model compression、expert fusion、efficient inference

Activation-Aware Low-Rank LLM Compression using Residual-Guided Sparse Correction Strategy

前瞻半導體研究所

大型語言模型、模型壓縮、奇異值分解、低秩近似、稀疏修正、訓練後壓縮、Large language models、Model compression、Singular value decomposition、Low-rank approximation、Sparse correction、Post-training compression

Low-Bit LLM Quantization via Salience-Aware Scale Search and Non-Uniform Grid Selection

電子研究所

大型語言模型、神經網路量化、權重量化、訓練後量化、非均勻量化、顯著性、Microscaling格式、Large Language Models、Neural Network Quantization、Weight Quantization、Post- Training Quantization、Non-Uniform Quantization、Salience、Microscaling Format

An Efficient LLM Inference Accelerator Supporting Golomb Decoding and Dynamic MX Quantization

電子研究所

大型語言模型、邊緣推論加速器、動態 MX 量化、Golomb 編碼、固定區塊長度壓縮、整數線性規劃、FPGA、Large Language Model、Edge Inference Accelerator、Dynamic MX Quantization、Golomb Coding、Fixed-Block-Length Compression、Integer Linear Programming

A Compact yet Accurate Nonlinear Function Unit Design Optimized for Microscaling Formats

電子研究所

非線性函數、Microscaling格式、exponential、Softmax、Sigmoid、Swish、Tanh、nonlinear function、Microscaling data formats

A Unified Model Compression Framework Supporting Multiple Weight Formats via Weight Packing

電子研究所

Huffman編碼、Golomb編碼、無損壓縮、大型語言模型、權重壓縮、權重封裝、Huffman Coding、Golomb Coding、Lossless Compression、Large Language Models、Weight Compression、Weight Packing

Hardware-Friendly Lossless Weight Compression Algorithms for Large Language Models

人工智慧技術與應用碩士學位學程

Huffman編碼、Golomb編碼、無損壓縮、大型語言模型、權重壓縮、Huffman Coding、Golomb Coding、Lossless Compression、Large Language Models、Weight Compression

An Efficient LLM Inference Accelerator with Asymmetric Quantization Optimized for Real-Time Edge Computing

電子研究所

硬體加速器、邊緣運算、Unified Dataflow、Transformer Decoder、向量運算引擎、大型語言模型、Hardware Accelerator、Edge Computing、Vector Processing Engine、Large Language Model

Microscaling Activation Quantization with Multiple Victims-Perpetrator Reordering Groups for LLMs

電子研究所

大型語言模型、神經網路量化、微縮格式、深度學習、混合精度量化、激勵值量化、Large Language Models、Neural Network Quantization、Microscaling Format、Deep Learning、Mixed-Precision Quantization、Activation Quantization

An Efficient End-to-End LLM Accelerator Supporting Dynamic Microscaling Quantization and Mixed-Precision Inference

電子研究所

硬體加速器、邊緣運算、大語言模型加速器、混精度運算、動態激勵值量化、MX-Format運算單元、及時問答聊天系統、Hardware Accelerator、Edge Computing、Language Model Accelerator、Mixed-Precision Computation、Dynamic Activation Quantization、MX-Format Processing Unit、Real-Time Question Answering System

SLM Embedding Table Compression and Placement for Memory Footprint and Latency Minimization

電子研究所

大型語言模型、小型語言模型、嵌入表、資料壓縮、深度學習、記憶體擺放、large language model、small language model、embedding table、data compression、deep learning、memory placement

A High-Performance FPGA Implementation for Edge LLM Inference Accelerator

電子研究所

大型語言模型、AXI Outstanding Transaction、高頻寬記憶體（HBM）、非對稱量化、AVX-512、Top-k 抽樣、大型語言模型推論加速、Large Language Model、High Bandwidth Memory (HBM)、Asymmetric Quantization、Top-k Sampling、LLM Inference Acceleration

A Pure Fixed-Point Quantization Framework Optimized for Low-Cost Edge Devices without Floating-Point Units

人工智慧技術與應用碩士學位學程

大型語言模型、神經網路量化、整數均勻量化、深度學習、硬體加速器、非對稱量化、純定點數量化、Large Language Models、Neural Network Quantization、Integer Uniform Quantization、Deep Learning、Hardware Accelerators、Asymmetric Quantization、Pure Fixed-Point Quantization

An Accurate and Compact Design Integrating Seven Common Nonlinear Functions in Deep Learning

電子研究所

Softmax、倒數、反平方根、reciprocal、inverse square root、Sigmoid、Swish、GELU、Tanh

An Efficient End-to-End Transformer Accelerator Supporting Window Attention and Pyramid Structure

電子研究所

硬體加速器、邊緣運算、Transformer神經網路、彈性矩陣分解、窗口注意力、卷積運算、非對稱量化、向量運算引擎、即時人像分割模型、人像分割背景疊合展示系統、hardware accelerator、edge computing、Transformer、flexible matrix decomposition、multi-operation fusion、window attention、convolution operation、asymmetric quantization、vector engine、real-time portrait segmentation demonstration system

Hardware-Aware Compression Technique on Randomly Accessible Tables through Adaptive Lossless Encoding and Lossy Quantization

電子研究所・共同指導：周景揚

隨機存取、嵌入表、壓縮、量化、編碼格式、位元重組、二階映射、random access、embedding table、compression、quantization、encoding format、bit-reshuffling、two-level mapping

An End-to-End Accelerator with Extremely High Resource Utilization for Both Convolution and Transformer Neural Network Models

電子研究所

卷積神經網路、Transformer神經網路、硬體加速器、非對稱量化、向量運算引擎、卷積地址產生器、即時手部姿態預測展示系統、convolutional neural networks、Transformer、hardware accelerator、asymmetric quantization、vector engine、convolution address generator、real-time hand pose estimation demonstration system

DDHNet: A Dense Data Honoring Neural Network Model for Click-Through Rate Prediction

電子研究所

推薦系統、點擊率預測、神經網路、深度學習、資料前處理、密集型資料、特徵交換、recommender system、click-through rate prediction、neural network、deep learning、data preprocessing、dense data、feature interaction

Automatic Design and Verification Methodology of Mixed-Signal System Considering Process Variation

電子研究所・共同指導：劉建男

製程變異、設計方法、架構辨識、電路優化、系統層級驗證、行為模型、良率分析、Process variation、design solution、structure recognition、circuit optimization、system-level verification、behavioral modeling、yield estimation

An All-MLP Neural Network Accelerator Design Supporting Asymmetric Quantization and Implicit Double Matrix Transpose

電子研究所

All-MLP神經網路、人工智慧、機器學習、硬體加速器、帶狀資料流、隱式雙重矩陣轉置、非對稱量化、圖像辨識展示系統、All-MLP neural network、artificial intelligence、machine learning、deep learning、hardware accelerator、strip-based dataflow、implicit double matrix transpose、asymmetric quantization、image classification demo system

A Highly Efficient Transformer Accelerator Supporting Implicit Matrix Transpose and Asymmetric Quantization

電子研究所

Transformer神經網路、硬體加速器、隱式矩陣轉置、非對稱量化、SRAM區塊排程與配置優化、及時姿態辨識系統、深度學習、Transformer、hardware accelerator、implicit matrix transpose、asymmetric quantization、SRAM block scheduling and allocation optimization、real-time pose estimation system、deep learning

Crafting Slim and Accurate Recommender Systems through Feature Condensation and Total Feature Interaction

電子研究所

推薦系統、點擊率預測、神經網路、深度學習、嵌入表、壓縮、特徵交互、recommender system、click-through rate prediction、neural network、deep learning、embedding table、compression、feature interaction、total interaction、high-order interaction

Embedding Table Compression in Recommender Systems via Index Condensation and Low-Bit Quantization

電子研究所・共同指導：周景揚

推薦系統、點擊率預測、嵌入表、模型壓縮、量化、權重共享、Recommender system、Click-Through Rate prediction、Embedding table、Model compression、Quantization、Weight sharing

Criticality-Driven Layer-Wise Pruning Algorithm for All-MLP Based Neural Network Models

電子研究所

神經網路、人工智慧、多層感知機、權重剪枝、可學習式稀疏度、Neural network、AI、Multilayer Perceptron、Weight pruning、Learnable sparsity

Performance Optimization for MLP Accelerators via ILP-Based Weight Allocation and Triple Activation Memory

電子研究所・共同指導：劉建男

多層感知機加速器、權重配置、效能優化、深度學習、整數線性規劃、MLP accelerator、weight allocation、performance optimization、deep learning、ILP

A Multiply-Accumulate (MAC) Unit Design Supporting 8-Bit Flexible Floating-Point (FFP8) Format

電子研究所

浮點數、乘加器設計、低精度運算、神經網路、人工智慧、Floating-point、Multiply-Accumulate (MAC) Unit Design、Low-precision computation、Neural network、AI

Hardware-Friendly Progressive Pruning for CNN Model Compression using Universal Pattern Sets

電子研究所

卷積神經網路、硬體加速器、模型壓縮、權重剪枝、樣式剪枝、通用樣式集、第一層剪枝、convolutional neural network、hardware accelerator、model compression、weight pruning、pattern pruning、universal pattern sets、first layer pruning

8-Bit Flexible Floating-Point Format for Accurate and Memory-Efficient Inference of Neural Networks

電子研究所

8位元浮點數格式、精度損失最小化、記憶體精省推論、深度學習、8-bit floating-point format、accuracy loss minimization、memory-efficient inference、deep learning

An SoC Integration Ready VLIW-Driven CNN Accelerator with High Utilization and Scalability

電子研究所

卷積神經網路、硬體加速器、低功耗、高資源使用率、高效能、單晶片系統整合、convolutional neural network、hardware accelerator、low power、high resource utilization、high performance、SoC integration ready

NNeed: An Evaluation and Design Space Exploration Engine for CNN Accelerators using Extensive Dataflow Analysis

電子研究所

卷積神經網路、硬體加速器、資料流、評估引擎、設計空間探索、convolution neural network、hardware accelerator、dataflow、evaluation engine、design space exploration

A Highly-Integrated Convolver Architecture Design using Depth-First Compression Scheme

電子研究所

卷積神經網路、硬體加速電路、卷積器設計、乘加運算、深度優先壓縮、部分積壓縮器、convolutional neural network、hardware accelerator、convolver design、multiply-accumulate operation、depth-first compression、compressor

Efficient and Low-Power MLP Accelerator Architecture Design Supporting Structured Pruning and Asymmetric Quantization for Edge Computing

電子研究所

多層感知機、模型壓縮、硬體加速器、軟硬體協同設計、multilayer perceptron、model compression、hardware accelerator、algorithm-hardware co-design

Low Accuracy Loss and Hardware-Friendly Model Compression Technique for DNNs

電子研究所

深度類神經網路、模型壓縮、硬體友善、Deep neural network、Model Compression、Hardware-friendly

Test Pattern Generation with High Fault Coverage for Irregular Digital Microfluidic Biochips

電子研究所

數位微流體生物晶片、測試、錯誤屏蔽效應、digital microfluidic biochip、testing、fault masking effect

A Dual-Convolver Based CNN Accelerator Achieving High Computing Resource Utilization

電子研究所

卷積神經網路、特殊應用積體電路、加速器、Convolutional Neural Network、ASIC、Accelerator

Sample Preparation for Reactant Minimization on MEDA-Based DMFBs using Partial Fraction Decomposition

電子研究所

樣本製備、微電極點陣列、數位微流體生物晶片、分數拆解法、Sample Preparation、Reactant Minimization、MEDA、DMFB、Partial Fraction Decomposition

Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on DMFBs

電子研究所

數位微流體生物晶片、儲存空間、貯槽換洗、排程技術、DMFBs、Storage、Reservoir Switching、Scheduling Algorithm

Probability-Based Sample Preparation for Unbalanced Splitting Correction on DMFBs

電子研究所

樣本製備程序、數位微流體生物晶片、分離不平衡、預測修正、修正需求、sample preparation、digital microfluidic biochip、unbalanced splitting、forecast-based correction、correction on demand

Time-Constrained Sample Preparation Algorithm for Reactant Minimization on DMFBs

電子研究所

數位微流體生物晶片、樣本製備技術、實驗室整合晶片、時間限制、反應物最小化、digital microfluidic biochip、sample preparation、lab-on-a-chip、time-constrained、reactant minimization

Thorough Defect Diagnosis for Reconfigurable Single-Electron Transistor Arrays

電子研究所

單電子電晶體、缺陷模型、缺陷診斷、診斷時間、single-electron transistors、defect model、defect diagnosis、diagnosis time

Many-Reactant and Multi-Target Sample Preparation on Flow-Based Microfluidic Biochips

電子研究所

樣本製備、微流道生物晶片、sample preparation、microfluidic biochip

Architecture Exploration and Delay Minimization Synthesis for SET-Based Field Programmable Gate Arrays

電子研究所

單電子電晶體、現場可程式邏輯閘陣列、延遲最小化、架構探索、single electron transistor、field programmable gate arrays、delay minimization、architecture exploration

Synthesis Technology for Reconfigurable Single-Electron Transistor Arrays

電子研究所

單電子電晶體、合成技術、可重構式架構、Single-Electron Transistor、synthesis technology、reconfigurable architecture

Defect-Aware Synthesis for Reconfigurable Single-Electron Transistor Arrays

電子研究所

單電子電晶體、缺陷感知、合成技術、single-electron transistor、defect-aware、synthesis

Many-Reactant Sample Preparation on Flow-Based Microfluidic Biochips

電子研究所

混合模型、樣本製備、微流道生物晶片、成本最小化、mixing model、sample preparation、flow-based microfluidic biochip (FMFB)、cost minimization

Volume-Oriented Sample Preparation for Reactant Minimization on Microfluidic Biochips with Multi-Segment Mixers

電子研究所

實驗室整合晶片、樣本製備程序、生物樣本最小化、反應物最小化、j微流道生物晶片、lab-on-a-chip、sample preparation、sample minimization、reactant minimization、flow-based microfluidic biochips

Multi-Target and Many-Reactant Sample Preparation for Reactant Minimization on DMFBs

電子工程學系 電子研究所

實驗室晶片、樣本製備技術、數位微流體生物晶片、多目標濃度及多反應物、Lab-on-a-Chip、Digital Microfluidic Biochip、Sample Preparation、Multi-target、Many-reactant

Synthesis for Reconfigurable Single-Electron Transistor Arrays Based on Traveling Salesman Problem Modeling

電子工程學系 電子研究所

單電子電晶體、自動化合成、可重組態架構、旅行推銷員問題、面積最小化、積項排序、single-electron transistor、automated synthesis、reconfigurable architectures、traveling salesman problem、area minimization、product term ordering

Multi-Objective Sample Preparation for Microfluidic Biochips with Various Mixing Models

電子工程學系 電子研究所

生物晶片、微流體晶片、樣本製備程序、多種混合模型、多目標最佳化、Lasb-on-a-chip(LoC)、microfluidic biochips、sample preparation、various mixing models、multi-objective optimization

A Study on Design Optimization of Three-Dimensional Integrated Circuits

電子工程學系 電子研究所

三維積體電路、直通矽穿孔、三維電路佈局、三維可程式邏輯閘陣列、熱感知擺放與繞線、3D ICs、through-silicon via (TSV)、3D floorplan、3D FPGAs、thermal-aware placement and routing

Sample Preparation on Microfluidic Biochips

電子工程學系 電子研究所

生物晶片、稀釋、稀釋樹、混合模式、數位微流體生物晶片、流式微流體生物晶片、反應物最小化、樣本製備、biochip、dilution、dilution tree、mixing model、digital microfluidic biochip (DMFB)、flow-based microfluidic biochip (FMFB)、reactant minimization、sample preparation

Variable ordering of binary decision diagram for product term reduction and its application to area minimization on single electron transistor arrays

電子工程學系 電子研究所

Single electron transistor、Single electron transistor array、Area minimization、Product term reduction、Binary decision diagram、Variable ordering、單電子電晶體、單電子電晶體陣列、面積最小化、乘積項縮減、二元決策圖、變數定序

Reactant Minimization for Sample Preparation on Microfluidic Biochips with Various Mixing Models

電子工程學系 電子研究所

生物晶片、稀釋、混合模型、反應物最小化、樣本製備程序、Biochip、Dilution、Mixing model、Reactant minimization、Sample preparation

Sample Preparation for Many-Reactant Bioassay on DMFBs using Common Dilution Operation Sharing

電子工程學系 電子研究所

樣本製備、多反應物、數位微流體生物晶片、共享稀釋操作、生物晶片、反應物用量最小化、sample preparation、many-reactant、digital microfluidic biochip (DMFB)、dilution operation sharing、biochip、reactant minimization

Area Minimization for CSA-Based Multiple Constant Multiplication Designs using Smart Sign Extension and Accurate Bit Counting

電子工程學系 電子研究所

多常數乘法、進位儲存加法器、位元計算、MCM、CSA、bit counting

Versatile Ring-Based Architecture for Digital Microfluidic Biochips and the Corresponding One-Pass Synthesis Algorithm

電子工程學系 電子研究所

數位微流體生物晶片、流體層級、多功能環狀架構、一站式合成、Digital microfluidic biochip、fluidic-level synthesis、chip-level design、one-pass synthesis

Topology similarity driven floorplan algorithm for wirelength minimization

電子工程學系 電子研究所

佈局、積體電路、floorplan、VLSI

Area minimization synthesis for reconfigurable single-electron transistor arrays with fabric constraints

電子工程學系 電子研究所

單電子電晶體、自動化合成、邏輯設計、可重組態架構、single-electron transistor、automated synthesis、logic design、reconfigurable architectures

A Parallel Layer-Aware Partitioning Algorithm for TSV Minimization in 3D ICs

電子工程學系 電子研究所

分割演算法、多核心、平行、partition、multi-core、parallel

Location-dependent thermal-aware 3D floorplan on general-purpose GPU

電子工程學系 電子研究所

佈局規劃、熱感知、floorplan、thermal-aware

High-Level Synthesis on Various Distributed Register Architectures

電子工程學系 電子研究所

高階合成、分散式暫存器架構、效能導向、位置感知、三維可程式邏輯陣列、架構探索、high-level synthesis、distributed-register archtecture、performace-driven、location-aware、3D FPGA、architectural exploration

Reactant and Waste Minimization in Multi-Target Sample Preparation on Digital Microfluidic Biochips

電子工程學系 電子研究所

數位微流體生物晶片、樣本製備程序、反應物最小化、廢液最小化、Digital Microfluidic Biochip、Sample Preparation、Reactant Minimization、Waste Minimization

High-Speed and Area-Minimized FIR Filter Design using Memory-Based Multiplication on FPGAs

電子工程學系 電子研究所

有限脈衝響應濾波器、記憶體式乘法器、可程式邏輯閘陣列、FIR filter、Memory-Based Multiplication、FPGA

Latency-Optimization Synthesis with Module Selection for Digital Microfluidic Biochips

電子工程學系 電子研究所

數位微流體晶片、高階合成、模組選擇、排程、儲存物最小化、合成、digital microfluidic biochip、high-levle synthesis、module selection、scheduling、storage minimization、synthesis

Efficient TSV Planning Algorithm via Congestion-Aware Block Shifting in 3D Floorplanning

電子工程學系 電子研究所

佈局、直通矽穿孔、三維積體電路、floorplan、TSV、3D IC

High-Level Synthesis with Degenerable Compound Functional Units for Delay Optimization

電子工程學系 電子研究所

高階合成、延遲最佳化、複合、功能單元、可退化的、High-Level Synthesis、delay optimization、compound、functional units、degenerable

Fault Tolerant Architectural Exploration and Fast Reconfiguration Algorithm for 3D FPGAs

電子工程學系 電子研究所

可程式化邏輯陣列、容錯、FPGA、Fault tolerant

Thermal-Aware Placement and Routing for 3D FPGAs

電子工程學系 電子研究所

熱感知、三維可程式邏輯閘陣列、擺放、繞線、熱模型、thermal-aware、3D FPGA、placement、routing、thermal model