劉建男

Interleaved Track Routing for Full-Around Shielding in High-Density Die-to-Die Interconnects

前瞻半導體研究所

先進封裝、晶片對晶片、信號完整性、全方位遮蔽、Advanced Packaging、Die-to-Die、Signal Integrity、Full-Around Shielding、Interleaved Track Routing

Localization-Guided Functional RTL Debugging with Large Language Models

國際半導體產業學院・共同指導：陳冠能

暫存器傳輸層級、功能性 RTL 除錯、錯誤定位、大型語言模型、自動化 RTL 修復、Register-Transfer Level、Functional RTL Debugging、Functional Error Localization、Large Language Models、Automated RTL Repair

Considering Signal Flow and Dummy Reduction During Guard Ring Sharing for Analog Layout Placement

電子研究所・共同指導：鄭耿璽

類比電路配置、保護環感知配置、訊號流、過渡虛設元件、analog placement、guard-ring-aware placement、signal flow、transition dummy

Non-Ideality-Aware Deep Neural Network Pruning for in-RRAM Computing Architectures

電子研究所

可變電阻式記憶體、記憶體內運算、結構化剪枝、硬體非理想效應、電壓降、熱效應、熱串擾、Resistive Random-Access Memory、In-Memory Computing、Structured Pruning、Hardware Non-Idealities、IR Drop、Thermal Effects、Thermal Crosstalk

GDIR: A Green Learning-Based Framework for Dynamic IR Drop Prediction

前瞻半導體研究所

動態壓降、綠色學習、離散餘弦轉換、電源完整性、資料高效率學習、Dynamic IR Drop、Green Learning、Discrete Cosine Transform、Power Integrity、Data-efficient Learning

Green Learning for DRV Prediction and Mitigation in Physical Design

電子研究所

綠色學習、設計規則違反預測、擺置精修、繞線導引、實體設計、電子設計自動化、機器學習、Green Learning、DRV Prediction、Placement Refinement、Routing Guidance、Physical Design、EDA、Machine Learning

Temperature-Aware Design Space Exploration Platform for Heterogeneous Computing System

電子研究所

設計空間探索、異質整合系統、晶粒架構、記憶體內運算、非理想效應、溫度感知模擬、design-space exploration、heterogeneous integration、chiplet architecture、computing-in-memory、non-ideal effects、temperature-aware simulation

Fast Insertion of Deep Trench Decoupling Capacitors in 2.5D Silicon Interposers for Power Integrity

前瞻半導體研究所

電源完整性、電源傳輸網路、去耦電容、矽中介層、目標阻抗、貪婪演算法、Sherman–Morrison 公式、power integrity、power delivery network、decoupling capacitor placement、silicon interposer、target impedance、greedy optimization、Sherman–Morrison formula

A Hierarchical Framework to Mitigate Non-Ideal Effects in Heterogeneous IRC Systems

電子研究所

記憶體內運算、行為模型、異質整合、電壓降、熱效應、Computing in memory、Behavioral model、Heterogeneous integration、IR-drop、Thermal effect

LLM-Assisted Interactive Analog IC Layout Automation

電子研究所

類比電路佈局、類比電路擺置、階層式B*-樹、大型語言模型、互動式佈局、提示詞工程、Analog Layout、Analog Placement、Hierarchical B*-Tree、Large Language Model、Interactive Layout、Prompt Engineering

Green Learning for Noise Prediction and Application on Routing Guidance Generation in IC Designs

國際半導體產業學院・共同指導：葉勝玄

綠色學習、繞線阻塞、串擾、耦合電容、繞線指引、噪音預測、Green Learning、Routing Congestion、Crosstalk、Coupling Capacitance、Routing Guidance、Noise Prediction

ANN-Based Initial Sample Transformation for Technology Migration in Analog Design

電子研究所

類比電路尺寸遷移、人工神經網絡、初始樣本轉移、製程變異、進化演算法、Analog circuit sizing migration、artificial neural networks、initial sample transformation、process variation、evolutionary algorithms

Analog Placement with Guard Ring Sharing Based on Hierarchical B*-Tree

電子研究所・共同指導：周景揚

類比電路擺置、類比電路佈局、電晶體陣列、保護環、階級式B*-tree、鰭式場效電晶體、analog placement、analog layout、transistor array、guard ring、hierarchical B*-tree、FinFET

ChimeSim: A System-Level Simulator for Chiplet-Based Memory-Centric Computing Architectures with Non-Ideal Effects

電子研究所

異質整合、近記憶體運算、記憶體內運算、熱效應、壓降效應、工作負載映射、Heterogeneous Integration、Near-Memory-Computing、Computing-In-Memory、Thermal、IR drop、Workload mapping

CORTEX: Cycle-Level RTL Power Estimation via Machine Learning with Thermal Awareness

電子研究所

RTL功耗估計、機器學習、滑動視窗、溫度感知建模、XGBoost、週期層級預測、VLSI設計、RTL powerestimation、machine learning、sliding window、thermal-aware modeling、cycle-level prediction、VLSI design

Weight Correction for Recovering Accuracy of Pruned Deep Neural Networks in Non-ideal RRAM Crossbars

電子研究所

電阻式記憶體、壓降、熱效應、熱串擾、權重校正、RRAM、IR-drop、Thermal Effect、Thermal Crosstalk、Weight Correction

Activity Aware Multibit Flip-Flop Regrouping with Self-Gating Insertion

電子研究所

多位正反器、正反器重組、自閘控、切換活動、低功耗、Multibit flip-flop、flip-flops regrouping、self-gating、switching activity、low power

Placement Refinement and Shielded Routing for Analog Circuit Layouts

電子研究所・共同指導：林柏宏

類比電路、佈線、屏蔽約束、Analog Circuit、Routing、Shielding Constraint

Initial Sample Transformation for the Automatic Sizing Engine in Analog Designs Migration

前瞻半導體研究所

類比電路尺寸遷移、初始樣本轉移、製程變異、進化演算法、alalog circuit sizing migration、initial sample transformation、process variation、evolutionary algorithm

IR-aware Weight Remapping Considering Thermal Effect and Stuck-at Faults in RRAM Crossbar Array

電子研究所

電阻式記憶體、壓降、電阻式記憶體內運算、固定型故障、熱效應、RRAM、IR-drop、in-RRAM computing、stuck-at fault、thermal effect

Obstacle-Aware Pin Assignment for Path Optimization in CDL-Based Routing Reconstruction

電子研究所

引腳指定、細部繞線、笛卡爾檢測線、Pin Assignment、Detailed Routing、Cartesian Detection Line

Machine Learning Assisted Net Parasitic Prediction in Custom Circuit Designs

電子研究所

寄生效應預測、線長預測、圖神經網路、全客製化電路設計、Parasitic Prediction、Wire Length Prediction、Graph Neural Network、Custom Circuit Design

Reinforcement Learning for Searching Worst Case in PVT Corner Analysis and Monte Carlo Simulation

前瞻半導體研究所

強化學習、製程變異、蒙地卡羅分析、角落分析、Reinforcement Learning、Process Variations、Monte Carlo Analysis、Corner Analysis

Crosstalk-Aware Routing Layer Assignment Using Graph Coloring in Analog Layout Design

電機資訊國際碩士學位學程

繞線層設定、串擾、圖著色、DSATUR算法、Layer Assignment、Crosstalk、Graph Coloring、DSATUR Algorithm

S-route Based Any-Angle Escape Routing for 2.5D Die-to-Die Connection with Offset Via

前瞻半導體研究所

D2D、偏移通孔、淚珠、逃逸繞線、S-route、offset via、teardrop、escape routing

ML-Assisted Cell Recipe Optimization for a Given Standard Cell Library

電子研究所

標準元件庫篩選、候選預測、效能優化、機器學習、數位電路設計、Standard cell library selection、Candidate prediction、Performance optimization、Machine learning、Digital circuit design

Transfer Learning in ML-Based Optimization Engine for Analog Circuit Migration Across Technology Nodes

電子研究所

製程變異、類比電路尺寸調整、進化演算法、機器學習、遷移學習、Process variation、analog circuit sizing、evolutionary algorithm、machine learning、transfer learning

Accurate Estimation of Buffered Interconnect Delay through Equation-based Virtual Buffering and Hierarchical Cluster Tree Techniques

電子研究所・共同指導：江蕙如

時序估計、虛擬緩衝器插入、緩衝器延遲估計、正交史坦納樹、Timing estimation、virtual buffering、buffer delay estimation、rectilinear Steiner tree

Fast Modeling of IR-drop Effects in RRAM Crossbar Arrays Considering Data Allocation

電子研究所

電阻式記憶體、壓降、電阻式記憶體內運算、RRAM、IR-drop、in-RRAM computing

Machine Learning Models for Net Parasitic and Wirelength Prediction in Custom Circuit Design at Schematic Level

電子研究所・共同指導：鄭耿璽

寄生效應預測、線長預測、圖神經網路、類比電路設計、parasitic estimation、wirelength estimation、graph neural network、analog design

Automatic Layout Synthesis Tool for Variation-Tolerant Boosted Buffer Circuit

國際半導體產業學院・共同指導：黃柏蒼

電路佈局自動化工具、使用者自定義佈局模板、Automated circuit layout tool、User-defined layout template

On Design Migration of Analog Building Block Library from Planar Transistor to FinFET

電子研究所

類比電路布局遷移、鰭式場效應電晶體、電路構建模塊資料庫、Analog circuit layout migration、FinFET、Circuit building block library

Sweepline-Based Algorithm for Layer Assignment on D2D Package Routing

電子研究所・共同指導：林柏宏

2.5D 集成電路、層分配、芯片對芯片封裝佈線、預分層、2.5D IC、layer assignment、die-to-die package routing、pre-layer assignment

A Routing Methodology Considering Pin Setting and Layer Assignment for Analog Layout Migration

電子研究所

類比電路佈局遷移、Analog layout migration

Automatic Design and Verification Methodology of Mixed-Signal System Considering Process Variation

電子研究所・共同指導：黃俊達

製程變異、設計方法、架構辨識、電路優化、系統層級驗證、行為模型、良率分析、Process variation、design solution、structure recognition、circuit optimization、system-level verification、behavioral modeling、yield estimation

A Fast Behavioral Model for ReRAM Crossbar Array to Support the Verification of In-Memory Computing Design

電子研究所・共同指導：林柏宏

電阻式記憶體、非理想效應、電阻式記憶體內運算、行為模型、ReRAM、non-ideal effect、in ReRAM computing、behavioral model

On Hardware Implementation Approach to Consider Body Effect in WDF-Based Circuit Emulator

電子研究所

混合訊號、波動數位濾波器、基體效應、Analog/mixed-signal (AMS)、Wave Digital Filter (WDF)、Body Effect

On Optimization of Key Components in an IMC System via Variation-aware ML-assisted Circuit Sizing Approach

電子研究所

類比電路尺寸調整、製程變異、機器學習、進化演算法、analog circuit sizing、process variation、machine learning、evolutionary algorithm

Performance Optimization for MLP Accelerators via ILP-Based Weight Allocation and Triple Activation Memory

電子研究所・共同指導：黃俊達

多層感知機加速器、權重配置、效能優化、深度學習、整數線性規劃、MLP accelerator、weight allocation、performance optimization、deep learning、ILP

Performance Oriented Automatic Analog Layout Synthesis Methodology

電子研究所・共同指導：陳宏明

類比電路佈局自動化、擺置、繞線、佈局遷移、序列對、Analog layout automation、Placement、Routing、Layout migration、Sequence pair

A Study on PLL Implementation Using WDF-Based Circuit Emulator

電子研究所・共同指導：周景揚

混合訊號、波動數位濾波器、鎖相迴路、程式化邏輯閘陣列、高層次合成技術、Analog/mixed-signal (AMS)、Wave Digital Filter (WDF)、Phase-Locked Loop (PLL)、Field Programmable Gate Array (FPGA)、High-Level Synthesis (HLS)

Fast Variation-aware Analog Circuit Sizing Approach with ML-Assisted Evolutionary Algorithm

電子研究所

製程變異、類比電路尺寸調整、進化演算法、機器學習、process variation、analog circuit sizing、evolutionary algorithm、machine learning

A Flexible Layout Migration Technique through Partial Learning

電子研究所

部分學習、類比電路佈局遷移、Parital learning、analog layout migration

Design Yield Analysis of SRAM-Based System with Peripheral Circuits

電子研究所・共同指導：賴伯承

製程變異、SRAM良率分析、周邊電路、記憶體內運算、蒙地卡羅分析、process variation、SRAM yield analysis、peripheral circuits、in-memory computing、Monte Carlo analysis

A Study on Congestion Refinement for Display Driver IC Layout

電子研究所・共同指導：陳宏明

實體設計、顯示器驅動、繞線擁擠、標準元件膨脹、模組擺放調整、Physical Design、Display Driver、Routing Congestion、Cell Inflation、Module Adjustment

A DRAM Data Mapping and Tiling Methodology on Sparse Convolution Neural Networks

電子研究所・共同指導：賴伯承

稀疏卷積神經網絡、動態隨機存取記憶體、資料擺放、sparse CNN、DRAM、data mapping

Coupling-Aware Behavioral Modeling for the Verification of In-SRAM Computing Design

電子研究所

行為模型、記憶體內運算、Behavioral Modeling、In-SRAM Computing

A Routing Methodology with Accurate Routing Resource Estimation for Analog Layout

電子研究所

電路佈局、實體設計、類比電路繞線、Circuit layout、Physical design、Analog routing

On Machine-Learning Assisted Evolutionary Algorithm for Analog Circuit Sizing with Parallel Computing

電子研究所

類比積體電路、元件參數調整、機器學習、進化演算法、平行演算法、analog circuit、device sizing、machine learning、evolutionary algorithm、parallel algorithm

An Irregular Power TSV Placement Algorithm for 3D IC

電子研究所・共同指導：陳宏明

矽穿孔、電源完整性、三維積體電路、電壓衰退、TSV、power integrity、3D IC、IR-drop

SVM-Based IR Drop Classification for Non-Uniform Power Delivery Network Analysis

電子研究所・共同指導：陳宏明

支持向量機、電路壓降、電源供應網路、SVM、support vector machine、IR drop、PDN、power delivery network

High Accuracy Behavioral Modeling of In-Memory Computing Design for AI Edge Applications

電子研究所

行為模型建立、記憶體內運算、混合訊號模擬、Behavior Modeling、Computation-in-memory、Mixed-signal simulation