黃柏蒼

A 16-nm Energy-Efficient Ternary-based LLM Accelerator with Sign-Guided Sparse Attention and Cross-Head Scheduling

前瞻半導體研究所

三值大型語言模型加速器、符號引導稀疏注意力、跨注意力頭排程、共用特殊功能單元、視覺 Transformer、Ternary LLM Accelerator、Sign-Guided Sparse Attention、Cross-Head Scheduling、Shared Special Function Unit、Vision Transformer

Distributed KV-Cache Management Units for anNear-Memory LLMAccelerator

國際半導體產業學院・共同指導：蘇育陞

大型語言模型、KV 快取、3D 堆疊 DRAM、近記憶體運算、分散式記憶體管理、Large Language Model、Distributed Memory Management、3D-Stacked DRAM、KV Cache、Processing-Near-Memory

Design of High Bit-Width FeRAM Array with Multi-read Deferred-Restore Scheme for Hyperdimensional Computing

國際半導體產業學院・共同指導：葉勝玄

鐵電隨機存取記憶體、1T1CFeRAM、多次讀取延後寫回、降低擾動讀取、單端感測放大器、高維度運算、Ferroelectric Random Access Memory、1T1C FeRAM、Multi-Read Deferred Restore、Reduced-Disturbance Read、Single-Ended Sense Amplifier、Hyperdimensional Computing、Associative Memory

Frozen-Bit LLR-Based Residual Carrier Frequency Offset Refinement for Polar-Coded Receivers

電子研究所・共同指導：周世傑

殘餘載波頻率偏移、解碼器輔助同步、凍結位元對數似然比總和（FBLS）、極化碼、連續消除列表解碼、Decoder-aided synchronization、frozen-bit LLR sum (FBLS)、polar codes、residual carrier frequency offset、successive-cancellation list decoding

Design and Implementation of a Low-Latency Wideband Swept-Spectrum Monitor for Interference-Aware Frequency-Hopping Systems

國際半導體人才教育專班・共同指導：蘇育陞

軟體定義無線電、USRP B210、FPGA 訊號處理、掃頻式頻譜監測、嵌入式邊緣運算、截獲機率、Software-Defined Radio、FPGA Signal Processing、Swept Spectrum Monitoring、Embedded Edge Computing、Probability of Intercept

Triple-Tier Monolithic 3D SRAM Design with Folded Topologies using Elevated-Laser-Liquid-Phase-Epitaxy Technology

國際半導體越南境外專班

單體式三維積體電路、階層式位元線、三維靜態隨機存取記憶體、高架式雷射液相磊晶、7奈米FinFET、M3D-IC、Hierarchical Bitline、3D-SRAM、Elevated-Laser-Liquid-Phase Epitaxy、7nm FinFET

A Transformer-Based Parameter Extraction Framework for BSIM-CMG Compact Model with Multi-Anchored Synthetic Data

國際半導體產業學院・共同指導：蘇育陞

BSIM-CMG、參數萃取、GAA、CFET、compact model、Differential Evolution、Transformer 神經網路、parameter extraction、compact modeling、Transformer neural network

Scalable FPGA-based Accelerator Design with Efficient Dataflow for YOLOv5m

電信工程研究所・共同指導：方凱田

YOLOv5m、FPGA加速、脈動陣列、資料重用、可擴展性、FPGA Acceleration、Systolic Array、Data Reuse、Scalability

Analytical Macro-Level Model and Dataflow-Aware Design Exploration for Digital Compute-in-Memory Architectures

國際半導體產業學院

數位記憶體內運算、分析模型、設計探索、資料流、模組分割、Digital Computing-in-Memory、Analytical Modeling、Design Space Exploration、Dataflow、Macro Partitioning

An All-Digital FeRAM-based In-Memory Similarity Search Engine with Multi-bit Exact Matching

國際半導體產業學院

鐵電隨機存取記憶體、內容可尋址記憶體、記憶體內搜尋、多位元精確比對、高維度運算、聯想記憶、Ferroelectric Random Access Memory (FeRAM)、Content-Addressable Memory (CAM)、In-Memory Search (IMS)、Multi-bit Exact Matching、Hyperdimensional Computing (HDC)、Associative Memory (AM)

An Automatic BSIM-CMG Parameter Extractor with Sensitivity-Driven Synthetic Data for GAA and CFET Technologies

前瞻半導體研究所

設計與技術協同優化、簡化模型校準、BSIM-CMG 參數萃取器、DTCO、Compact Model Calibration、BSIM-CMG Parameter Extractor

A 16nm 0.708 TOPS/mm² BitNet Accelerator with Hybrid Ternary-Booth Multipliers for Efficient Autoregressive Inference

國際半導體產業學院

終端運算、硬體加速器、大語言模型加速器、激勵值量化、自回歸模型、Edge Computing、Hardware Accelerator、Large Language Model (LLM) Accelerator、Mixed-Precision Computation、Activation Quantization

CFeFET-based Progressive Hyperdimensional In-Memory Search Engine

前瞻半導體研究所

高維度向量運算、布斯乘法演算法、卷積神經網路、互補式鐵電電晶體、數位記憶體內運算、hyperdimensional computing、convolutional neural networks、complementary ferroelectric transistor、Booth's multiplication algorithm、digital in-memory computing

5μs Ultra-low-latency Joint Time-Frequency Synchronization Module Design for Wireless Mesh Network with Frequency Hopping

電子研究所・共同指導：周世傑

跳頻、單載波、數位基頻收發機、同步、都卜勒效應、載波頻率偏移、符元時序偏移、Frequency hopping、Single carrier、Digital baseband transceiver、Synchronization、Doppler effect、Carrier frequency offset、Symbol timing offset

Fault-Tolerant Methods for Distributed 3D-Stacked DRAM Controllers in DRAM-on-Logic Near-Memory Computing

國際半導體產業學院

三維堆疊動態隨機存取記憶體、記憶體邏輯層整合、容錯設計、內建備援分析、錯誤更正碼、記憶體控制器、3D-Stacked DRAM、DRAM-on-Logic、Fault Tolerance、Built-In Redundancy Analysis、Error Correction Code、Memory Controller

Distributed 3D-Stacked DRAM Controller for Processing-Near-Memory AI Accelerator

國際半導體產業學院・共同指導：葉勝玄

三維堆疊DRAM記憶體、架構模擬器、記憶體控制器、DRAM自刷新、AI加速器、3D-Stacked DRAM、Architectural Simulator、Memory Controller、DRAM Refresh、AI Accelerator

Variation-tolerant and Noise-Immune Content-Addressable Memory Design using Complementary FeFET

國際半導體產業學院・共同指導：葉勝玄

互補式鐵電記憶體、內容定址記憶體、記憶體內運算、動態電路、抗雜訊能力、電路穩健性、製程變異、動態雜訊指標、Complementary FeFET、Content Addressable Memory、Ternary Content Addressable Memory、In-Memory Computing、Dynamic Circuit、Noise Immunity、Process Variation、Dynamic Noise Metric

Module-Based SRAM Virtual Compiler for Early-Phase Customized Diagnosis

國際半導體產業學院・共同指導：葉勝玄

SRAM虛擬編譯器、客製模組化電路、靜態隨機存取記憶體、電路診斷、錯誤模型、SRAM Virtual Compiler、Custom Modular Circuit、Fault Model、Static Random-Access Memory、Circuit Diagnosis

16nm Area-Efficient Accelerator Design with 3D-DRAM and Bank-Level Dataflow Optimization for Diffusion Models

國際半導體產業學院

三維動態隨機存取記憶體加速器、擴散模型、資料流最佳化、庫級資料管理、設計空間探索、3D-DRAM Accelerator、Diffusion Models、Dataflow Optimization、Bank level Data Management、Design Space Exploration

Analytical Model and Design Exploration of Digital Computing-In-Memory Macros

前瞻半導體研究所

數位記憶體內運算、分析模型、設計探索、DCIM模組整合、Digital Computing-In-Memory、Analytical Model、Design Exploration、DCIM Macro-Level Integration

Flexible and Energy-Efficient Interconnection Architectures with 3D-SRAM and Embedded Active bridge Chipset for Memory-intensive AI applications

電子研究所・共同指導：陳宏明

3.5D整合技術、彈性節能三維連線架構、嵌入式多晶片主動橋接晶片組、三維靜態記憶體、神經網路加速器、3.5D Integration、3D interconnection architecture、EMAB chipset、3D-SRAM、DNN accelerator

High-Density Dual-Layer 3D-SRAM Array with Si-pillar-aware partition and shared Bitline scheme using Monolithic 3D Elevated-Epi Technique

國際半導體產業學院・共同指導：葉勝玄

積層型三維技術、雷射液態磊晶、靜態隨機存取記憶體、矽柱考慮分區、共享位線方案、Monolithic 3D integration、Laser-Liquid-Phase-Epitaxy、3D-SRAM、Silicon-pillar-aware design、Shared bitline

Non-Linear Tunable RO-based Time-to-Digital Converter for FeFET-based Computation-in-Memory Macro

前瞻半導體研究所

記憶體內運算、時間數位轉換器、可變式環形震盪器、鐵電晶體、抵抗 PVT的變異、Computing-in-Memory、Time-to-Digital Converter、Tunable Ring Oscillator、Ferroelectric FET、Anti-PVT variation

Energy-Efficient In-Memory Retrieval Engine with Compressed Hyperdimensional Computing Techniques

前瞻半導體研究所

多維度向量運算、互補式鐵電電晶體、漢明距離、加法樹、數位記憶體內、hyperdimensional computing(HDC)、complementary ferroelectric transistor (CFeFET)、Hamming distance、adder tree、digital in-memory computing

An Efficient Digital Computation-in-Memory (D-CIM) Macro with Approximate Adder Tree using 16nm FinFET Technology

國際半導體產業學院・共同指導：葉勝玄

數位記憶體內運算、加法樹、近似運算、低功耗、8T靜態隨機存取記憶體、Digital Computation-in-Memory、adder tree、approximate computation、low power、8T static random-access memory (SRAM)

Irregular Operation-Unit-based Compression for Non-Volatile Computation-in-Memory Accelerator

國際半導體產業學院

神經網絡、非揮發性記憶體、操作單元、稀疏性、聚類問題、Neural network、Non-volatile memory、Operation Unit、Sparsity、Clustering problem

Beyond Speed: Low-latency And Sustainable Solutions For mmWave Communications And FMCW Radar Systems

國際半導體產業學院

波束精化、毫米波、節能、稀疏快速傅里葉變換、壓縮感知、beam-refinement、millimeter wave、energy-efficient、sparse fast fourier transform、compressed sensing

Energy-Efficient All-Digital Computation-in-Memory Macro Design with CFeFET-based Booth Decoder

國際半導體產業學院

數位記憶體內運算、布斯乘法演算法、鐵電晶體、摺疊架構、電壓調節、Digital computing-in-memory、Booth's multiplication algorithm、Complementary Ferroelectric FETs、Folded architecture、Voltage scaling

On Die-to-die Routing Methodology for Fan-out Packages

國際半導體產業學院・共同指導：陳宏明

重新分佈層路由、細部繞線、扇出封裝、差分對、共平面波導、自由分配繞線、芯片對芯片繞線、Redistribution layer routing、Detailed Routing、Fan-out package、Differential Pair、Coplanar waveguide (CPWG) routing、Free-assigned routing、Die-to-die routing

Framework and Design Exploration of In-Situ Error Correction for Multi-Bit Computation-in-Memory Circuits

國際半導體產業學院

記憶體內運算、多位元權重拆解、硬體錯誤分析、In-Situ錯誤更正、鉗夾策略、Computation-in-memory、Multi-bit weight decomposition、Hardware error analysis、In-situ error correction、Clamping strategy

Energy-Efficient Digital Floating-Point Computation-in-Memory Macro Design with Flexible Blocks using 16nm FinFET Technology

國際半導體產業學院

數位記憶體內運算、分時多工、布斯演算法、加法樹、塊浮點數、Digital Computation-in-Memory、time-division multiplexing、Booth algorithm、adder tree、Block floating point

A 28nm Row-based Pipelined Accelerator with Multi-bank Buffer Management for On-Device Transfer Learning

國際半導體產業學院

邊緣裝置運算、終端裝置運算、卷積神經網路訓練、訓練加速器、模擬量化、Multi-bank 記憶體管理、On-Device Training、Training Accelerator、CNN Training、Simulated Quantization、Multi-bank Memory Management

Programmable Capacitive Sensor Array with Ts-TDC Architecture for Cell Detection

國際半導體產業學院・共同指導：李鎮宜

CMOS 實驗室晶片、電容感測陣列、時序共享之時間數位轉換、CMOS Lab-On-Chip (LOC)、Capacitive Sensor Array (CSA)、ts-TDC

Monolithic Hybrid-3D Standard Cell Library with Sandwiched Inter-Metal Layer for 3D Digital Computation-in-Memory Circuits

國際半導體產業學院

混合式三維標準元件庫、Monolithic、Hybrid-3D、Standard、Cell、Library

Distributed Digital Voltage Regulation with Predicted Control for Cache in 3D NAND Flash

國際半導體產業學院

數位電源穩壓器、分散式穩壓電路、電流預測機制、電流斜率偵測、粗調與細調控制、Digital LDO、Distributed Voltage Regulation、Current Prediction、Slope detection、Coarse-Fine tuning control

A 28nm Vision Transformer Accelerater with Integer-Only Quantized Attention Block

國際半導體產業學院

視覺轉換器、終端裝置運算、模擬量化、整數量化、加速器、Vision Transformer、ViT、On-Device Inference、Simulated Quantization、Integer-Only Quantization、Accelerator

Automatic Layout Synthesis Tool for Variation-Tolerant Boosted Buffer Circuit

國際半導體產業學院・共同指導：劉建男

電路佈局自動化工具、使用者自定義佈局模板、Automated circuit layout tool、User-defined layout template

High-Speed Cache Design with Hierarchal Single-ended Read Scheme for 3D NAND Flash

國際半導體產業學院

高速記憶體、階層式單端讀取、3D Flash、Cache

Energy-Efficient Digital Computation-in-Memory Macro Design with Customized Extended Standard Cells using 16nm FinFET Technology

國際半導體產業學院

數位記憶體內運算、分時多工、布斯演算法、客製化擴充標準單元、加法樹、Computation-in-Memory、time-division multiplexing、Booth algorithm、customized extended standard cells、adder tree

Energy-Efficient Digital Computation-in-Memory Macro Design with Irregular Lookup Table using Complementary Ferroelectric FETs

國際半導體產業學院

鐵電電晶體、互補式鐵電電晶體、數位式記憶體內運算、不規則查表電路、FeFET、Complementary FeFET、Digital Computation-in-Memory、Irregular Lookup Table

Low-Voltage Single-Ended Signaling with DECAP Allocation and Phase Coding for 3DICs

電子研究所・共同指導：陳宏明

矽穿孔、靜電防護、低電壓擺幅、去耦電容、相位編碼、串擾減少、Through Silicon Via、Electrostatic Discharge、Low Voltage Swing、Decoupling capacitor、Phase Coding、Crosstalk Reduction

An Energy-efficient Row-Based Pipelined CNN Training Accelerator for On-Device Transfer Learning with Simulated Quantization

國際半導體產業學院

卷積神經網路、邊緣裝置學習、模擬量化、遷移學習、訓練加速器、CNN training、On-device training、Simulated quantization、Transfer learning、Training accelerator

Monolithic 3D Digital computation-in-memory circuits with hybrid-3D standard cells using Laser-Liquid-Phase-Epitaxy Technique

國際半導體產業學院

三維積體、雷射液態磊晶、單晶、記憶體內運算電路、積層型中段製程電路、3D-IC、Laser-Liquid-Phase-Epitaxy、Single-Crystal、Computation-In-Memory circuits、Middle-end of line (MEOL) circuits

Area and Power Efficient TDC for SPAD Image Application

國際半導體產業學院・共同指導：李鎮宜

時間數位轉換器、面積和功率優化、環形振盪器、單光子崩潰二極體、整倍數延遲鎖相電路、Time­-to-­Digital Converter (TDC)、Area and power efficient、Ring Oscillator (RO)、Single ­Photon Avalanche Diode (SPAD)、Multiplying Delay ­Locked Loop (MDLL)

Fast Early-phase Predictive Placer Using Cross-platform Acceleration Framework

國際半導體產業學院

可解析擺置器、GPU 加速的擺放演算法、CPU 平行化技巧、跨平台加速的架構、稀疏矩陣格式、analytical placement、GPU-accelerated placement、CPU parallel technique、crossplatform acceleration framework、SPARSE matrix format ii

Variation-Tolerant Capacitive Boosted Buffer Design using Monolithic 3D-IC BEOL FinFETs

國際半導體產業學院

積層型三維積體電路、低功耗電路設計、增壓緩衝器、製程變異容忍、monolithic 3D IC technology、low power circuit design、boosted buffer、variation-tolerant

Energy-Efficient Digital Computation-in-Memory Design with Adaptive Floating Point for Deep Neural Networks

國際半導體產業學院

數位記憶體內運算、分時多工、自適應浮點數、摺疊架構、時序交錯、Digital computation-in-memory、Time division multiplexing、Adaptive floating point、folded architecture、time interleaving

Crystal-orientation-Tolerant Design Techniques for Monolithic 3D SRAM and LDO with Single-Crystal-Islands

國際半導體產業學院

穩壓器、靜態隨機存取記憶體、三維積體、晶粒邊界、單晶矽島、LDO、SRAM、3DIC、Grain boundary、Single-Crystal-Island

Precision-Aware Workload Distribution and Dataflow for a Hybrid Digital-CIM Deep CNN Accelerator

國際半導體產業學院

記憶體內運算、卷積神經網路、低功耗、精準度感知工作分配、hybrid digital-CIM、CNN、precision-aware、energy efficiency

A Variation-Tolerant Deep Learning Training Framework for Emerging Computation-in-Memory Circuits

國際半導體產業學院

深度學習、神經網路訓練框架、突觸單元變異性、Neuromorphic、Training Framework、Variability、Neural Networks

Active DECAPs with Region-based Current Prediction for Dynamic Noise Suppression in TSV 3DICs

國際半導體產業學院

主動式去耦合電容、電流預測、三維積體電路、電源雜訊動態抑制、active DECAP、current profile prediction、TSV 3DICs、Dynamic Noise Suppression

Cognitive Bus Coding Scheme for Inter-Chip Communications on Low-cost Si or Glass Interposers

國際半導體產業學院

CAC、分碼多重進接、匯流排編碼、訊號完整性、晶片間通信、CDMA、bus coding、signal integrity、inter-chip communication

Crystal-Orientation-Tolerant Voltage Regulator using Monolithic 3D BEOL FinFETs in Single-Crystal Islands for On-Chip Power Delivery Network

國際半導體產業學院

積層型三維積體電路、數位線性穩壓器、單晶島內後製程、三維數位線性穩壓器、晶向變異容忍電源閘單元配置、Monolithic 3D-IC、Digital LDO、BEOL FinFETs in single-crystal islands、3D LDO、crystal-orientation-tolerant PG-cell allocation

An All-digital Wideband OFDM-based Frequency-hopping System using RF Sampling Data Converters

國際半導體產業學院

射頻取樣、正交分頻多工、跳頻、RF Sampling Receiver、OFDM、Frequency-hopping

Power Noise Suppression Design Methodology using Active Decoupling Capacitors for TSV 3DIC

電子研究所・共同指導：陳宏明

三維矽穿孔、主動式去耦電容、電源雜訊、TSV 3DIC、Active Decoupling Capacitor、Power Noise

A Fast-Response Hybrid-Searching Fully-Integrated LDO using Monolithic 3D IC Technology

國際半導體產業學院

積層型三維積體電路、數位線性穩壓器、局部晶格控制技術、Monolithic 3D IC、Digital LDO、Location-controlled grain

Reducing Impacts of Speckle on Color Holographic Head-up Display by Time-Division Multiplexing Method

電機學院電子與光電學程・共同指導：黃乙白

全像投影、彩色全像投影、時間多工、光斑消除、Hologram、Color hologram、TDM、Reduce speckle

Variable-length Sparse 2D Fast Fourier Transform Accelerator for High-Speed mmWave Radar Applications

電機學院電信學程・共同指導：王蒞君

可變點數稀疏快速傅立葉轉換、Variable-length Sparse 2D Fast Fourier Transform

SRAM Variation Analysis and Peripheral R/W-Assist Circuits using Monolithic 3D BEOL FinFET Circuits

國際半導體產業學院

積層型三維積體電路、靜態隨機存取記憶體、讀寫輔助電路、Monolithic 3D-IC、SRAM、read/write-assist circuit

Fast-Response Digital Linear Voltage Regulator with Time-Sharing and Double-Edge-Triggered Techniques using Monolithic 3D IC

電子研究所・共同指導：溫瓌岸

數位線性穩壓器、積層型三維積體電路、Digitally Linear Voltage Regulator、Monolithic 3D-IC