陳宏明

Learning-Guided Via Placement for Fast Rip-up Routing of Dense Die-to-Die Interconnects

前瞻半導體研究所

先進封裝、晶粒間互連、重佈線層繞線、通孔配置、拆線重佈、擴散模型、機器學習輔助電子設計自動化、Advanced Packaging、Die-to-Die Interconnect、Redistribution Layer Routing、Via Placement、Rip-up-and-Reroute、Diffusion Model、Machine Learning for EDA

3T NSFET Standard Cell Layout Synthesis with Graph-Guided Placement and ILP-Based 2D Routing

電子研究所

奈米片場效電晶體、自動化、3T 標準單元、標準單元版圖合成、佈局擺置、二維繞線、數線性規劃、automatic、NSFET、3T standard cell、standard-cell layout synthesis、placement、2D routing、integer linear programming

Routability-Driven SAT-Filtered Beam Search Placement for Industrial Standard Cell Library in Advanced NSFETs

電子研究所

奈米片場效電晶體、標準元件庫、佈局擺置、集束搜尋、SAT過濾器、尤拉面積估計、雍塞估計、Nanosheet FET、Standard Cell Library、Placement、Beam Search、SAT Filter、Euler Area estimation、Congestion Estimation

Concurrent Multi-SoC Chiplet Partitioning, Technology Assignment and Placement

電子研究所

2.5D 積體電路、小晶片分割、製程指派、模擬退火、階層式 B*-樹、小晶片重用、2.5D ICs、Chiplet Partitioning、Technology Assignment、Simulated Annealing、Hierarchical B*-tree、Chiplet Reuse

CLS: A Closed-Loop Skill-Based LLM Framework for Interactive Analog IC Layout Design

管理學院專班-工業工程與管理學程・共同指導：劉建良

類比積體電路佈局、大型語言模型、閉迴路技能式框架、意圖分派、技能式解析、佈局指標回饋、Analog IC layout、Large Language Models、closed-loop skill-based framework、intent dispatch、skill-based parsing、layout-metric feedback

A Study for Programmable Package Customized Layer Layout Design and Pin Assignment

電機工程學系・共同指導：張文輝

實體設計、繞線、自動化、異質整合、可程式預製基板、Physical Design、Routing、Automation、Heterogeneous Integration、Programmable Substrate

Training-Free CCS Library Generation via Voltage Domain Transformation and PCHIP Interpolation

資訊學院碩士在職專班・共同指導：許騰尹

CCS時序庫、PVT變異、電壓域建模、PCHIP、免訓練方法、CCS timing library、PVT variation、Voltage-domain interpolation、Training-free modeling

Pre-Layout Decap Planning for Interposer-Based 3DICs

電子研究所

3D 積體電路電容布局、中介層、基因演算法、布局前設計、整數線性規劃、3D IC Decap Placement、Interposer、Genetic Algorithm、Pre-Layout、Integer Linear Programming

On Generating Efficient Double-Row CFET Cells Through DP-Based Placement and MCF Routing

電子研究所

雙列、互補式場效電晶體、標準元件庫、電晶體佈局、元件內繞線、多物網路流、整數線性規劃、Double-row、CFET、Standard cell library、Transistor placement、In-cell routing、Multi-commodity flow、Integer linear programming

ILP-based synthesis study of optical loss minimization in photonic circuits

電子研究所

光子積體電路、整數線性規劃、自動佈局繞線、A*搜索演算法、波導繞線、光損耗最小化、Photonic Integrated Circuits (PICs)、Integer Linear Programming (ILP)、Automatic Placement and Routing (APR)、A*Search Algorithm、Waveguide Routing、Optical Loss Minimization

Reinforcement Learning-Based Clock Tree Parameter Optimization with Graph Neural Networks

電子研究所

時鐘樹、強化學習、圖注意力網路、最大偏斜、延遲時間、Clock Tree、Reinforcement Learning、Graph Attention Network(GAT)、Soft Actor-Critic(SAC)、Maximum Skew、Slew Time

On Generating NSFET Standard Cell Library with DP-Based Placement and ILP-Based MCF Routing

電子研究所

奈米片電晶體、標準單元庫、佈局擺置、佈線、整數線性規劃、多物網路流、Nanosheet FET、Standard cell library、Placement、Routing、Integer linear programming、Multi-commodity flow

On Generating CFET Cells with MCF and DP-Based Layout Planning

電子研究所

標準元件庫、擺置、繞線、多商品流、自動化、互補式堆疊場效電晶體、standard cell library、placement、routing、multi-commodity flow、automation、complementary field-effect transistor

Early FPGA-Failure Detection In Multi-FPGA Emulation System Using Neural Network

電子研究所

多FPGA仿真、佈線壅塞、深度學習、Multi-FPGA Emulation、Routing Congestion、Deep Learning

A Deep Reinforcement Learning Structure for PPO-Based Global Routing

電機資訊國際碩士學位學程

VLSI 全域繞線、二腳位網路繞線、DQN、Proximal Policy Optimization (PPO)、強化學習、壅塞感知繞線、繞線環境模擬、VLSI Global Routing、Two-Pin Net Routing、Reinforcement Learning、Congestion-Aware Routing、Routing Environment Simulation

A Thermal- and Timing-Aware Approach to 2.5D-IC Chiplet Placement

電子研究所

2.5D積體電路、小晶片佈局、熱感知佈局、時序感知最佳化、多目標最佳化、2.5D IC、chiplet placement、thermal-aware placement、timing-aware optimization、multi-objective optimization

Learning-Based Thermal Prediction in Modern Advanced Packaging

電子研究所

深度學習、2.5D封裝、熱分析、Deep learning、Attention、FiLM (Feature-wise Linear Modulation)、U-Net、2.5D packaging、Thermal analysis

Integrated Thermal-Aware Partitioning and Placement Optimization for 3D IC Design

資訊學院碩士在職專班・共同指導：李毅郎

整數線性規劃、矽穿孔、三維積體電路分割、三維積體電路擺置、熱感知、Integer Linear Programming、Through Silicon Via、3D IC partition、3D IC placement、Thermal Aware

A Weight-Based Multibit Flip-Flop Banking Framework for Configurable Power, Performance, and Area Co-Optimization

電子研究所・共同指導：林柏宏

多位元正反器、MBFF 合併、正反器叢集、動態功耗、Multibit flip-flop、MBFF banking、flip-flop clustering、dynamic power

RL-based 2.5D IC RDLs Offset-Via and Teardrop Assignment

電子研究所・共同指導：賴伯承

2.5D積體電路重分佈層、偏移通孔、淚滴結構、強化學習—近端策略優化演算法、圖注意力網路、2.5D IC Redistribution Layer (RDL)、Offset-Via、Teardrop Structure、Reinforcement Learning–Proximal Policy Optimization (PPO)、Graph Attention Network (GAT)

Flexible and Energy-Efficient Interconnection Architectures with 3D-SRAM and Embedded Active bridge Chipset for Memory-intensive AI applications

電子研究所・共同指導：黃柏蒼

3.5D整合技術、彈性節能三維連線架構、嵌入式多晶片主動橋接晶片組、三維靜態記憶體、神經網路加速器、3.5D Integration、3D interconnection architecture、EMAB chipset、3D-SRAM、DNN accelerator

An Implementation of Hierarchical-Constraint-Aware Layout Refinement on Commercial Layout Editor

電子研究所・共同指導：賴伯承

類比電路佈局、設計自動化、類比電路擺置、對稱、階層、analog layout、design automation、analog placement、symmetry、hierarchy

Gate-Level Hardware Trojan Detection via Heterogeneous Graph Attention Network

資訊安全研究所

硬體安全、硬體木馬檢測、異構圖、深度學習、圖神經網絡、異構圖注意力網路、Hardware Security、Hardware Trojan Detection、Heterogeneous Graph、Deep Learning、Graph Neural Network、Heterogeneous Graph Attention Network

On Commercial FinFET Cell Library Generation Via ILP and DRC Report

前瞻半導體研究所

16nm FinFET 技術、標準單元、模擬退火、ILP、16nm FinFET Technology、standard cell、Simulated Annealing

Evaluating Signal Integrity in InFO Package via Learning-based Methods

國際半導體產業學院・共同指導：陳冠能

訊號完整度、InFO封裝、第三代高頻寬記憶體、XGBoost、LightGBM、Gurobi最佳化器、Signal Integrity、InFO Package、High Bandwidth Memory 3、Gurobi Optimizer

Dynamic Path Planning for FPGA Routing: A congestion-Aware and Capacity-Adaptive Approach

前瞻半導體研究所

繞線優化、動態擁塞監控、成本函數調整、現場可程式化邏輯閘陣列、FPGA、routing optimization、dynamic congestion monitoring、cost adjustment

Reinforcement Learning-Based Floorplanning with Rectilinear Outline

人工智慧技術與應用碩士學位學程

佈局設計、強化學習、集群模組、正交模組、序列對、Floorplanning、reinforcement learning、clustering modules、rectilinear modules、sequence-pair

Floorplanning for Modern Hierarchical Design Modules: Minimization of Whitespace and Clustering Constraint Violations

電子研究所

平面規劃、階層式設計、集群限制、降低空白區域、正交多邊形模組、Floorplanning、Hierarchical design、Clustering constraint、Whitespace reduction、Rectilinear module

Learning-based Crosstalk Prediction on Fanout Package Designs

人工智慧技術與應用碩士學位學程

深度學習、串音、U型網路、3D卷積神經網路、Deep learning、Crosstalk、U-Net、3D-CNN

Flow and Regression Based Any-Angle Routing on Chiplets with Offset Via Awareness

電子研究所

偏移通孔、淚珠、2.5DIC、網路流、線性回歸、offset via、teardrop、2.5D IC、network-flow、linear regression

A Study on Implementing Reinforcement Learning based Fixed-Outline Floorplanning

網路工程研究所・共同指導：李毅郎

佈局設計、強化學習、序列對、模擬退火、Floorplanning、Reinforcement Learning、Sequence-Pair、Simulated Annealing

Dynamic Programming-Based Clock Tree Synthesis for Low Jitter in High-Speed ADC System

電子研究所

時鐘樹合成、時鐘抖動、動態規劃、高速類比數位轉換器、非直角繞線、clock tree synthesis、clock jitter、dynamic programming、memoization、high- speed ADCs、non-rectilinear routing

On Complex Monolithic Stacked FinFET Cells Generation using ASAP7 Technology

電子研究所

單片式三維、鰭式場效電晶體、擺放、繞線、自動化、Monolithic 3D、FinFET、Placement、Routing、Automatic

On Generating Homogeneous Multi-Gate Monolithic Stacked FinFET Cells

電子研究所・共同指導：郭建男

多閘門、自動化、擺置、繞線、線性方程式、multi-gate、automation、placement、routing、linear equation

On Die-to-die Routing Methodology for Fan-out Packages

國際半導體產業學院・共同指導：黃柏蒼

重新分佈層路由、細部繞線、扇出封裝、差分對、共平面波導、自由分配繞線、芯片對芯片繞線、Redistribution layer routing、Detailed Routing、Fan-out package、Differential Pair、Coplanar waveguide (CPWG) routing、Free-assigned routing、Die-to-die routing

Die-to-Die Multiple Redistribution Layer Global Routing with Offset-Via

前瞻半導體研究所

InFo_oS、繞線、自動化、任意角度、屏蔽、routing、automatic、any-angle、shielding

On Generating Monolithic Stacked FinFET Cell Library

電子研究所

標準單元庫、單片式 3D、鰭式場效電晶體、放置、動態規劃、布線、多商品 流、自動化、standard cell library、monolithic 3D、FinFET、placement、dynamic program ming、routing、multi commodity flow、automatic

3D IC Thermal Aware Layer Partitioning and Placement with Heat Sink Efficiency Analysis

電子研究所

三維積體電路分割、三維積體電路擺置、矽穿孔、熱模型、有限差分法、3D IC partition、Through Silicon Via、thermal model、finite difference method

Commercial FinFET Layout Migrations for Additional Design Rules

電子研究所

鰭式場效應電晶體、單元佈局、遷移、隅角編織法、約束圖、設計 則、標準單元庫、FinFET、cell layout、migration、corner stitching、constraint graph、standard cell library、design rules

Performance-Aware Analog Placement and Continuous OD Clustered Transistor Array Modules Generation for Fully Symmetric Analog Circuits

電子研究所

擺置、電晶體陣列、擴散區共用、連續擴散區、佈局依賴效應、自動化、placement、transistor array、diffusion sharing、continuous OD、layout-dependent effects、automatic

Analog Layout Optimization by Custom Partitioning and Placement

電子研究所

電阻式隨機存取記憶、記憶體內運算、類比電路佈局、自動化、佈圖擺置、resistive random-access memory、computing-in-memory、analog circuit layout、automation、placement

On Efficient Analog Template Layout Generation for High Accuracy and Performance Nanometer Circuits

電子研究所・共同指導：江蕙如

模擬佈局生成、模板基礎方法、高品質佈局、平面規劃、無網格繞線、自動化、時鐘樹合成、analog layout generation、template-based approach、high-quality layouts、floorplan、gridless router、automatic、clock tree synthesis

ML/DL-based Signal Integrity Optimization for InFO Any-angle Routing

國際半導體產業學院・共同指導：吳添立

訊號完整性、CatBoost、深度神經網路、第三代高頻寬記憶體、InFO 任意角度繞線、Signal Integrity、DNN、HBM3、InFO Any-angle Routing

A Software-Hardware Co-Optimized Accelerator Architecture for Graph Convolutional Networks

電子研究所・共同指導：賴伯承

圖神經網路、軟硬體協同設計、高階合成、高頻寬記憶體、硬體加速、Graph Neural Network、Software-Hardware Co-Design、High Level Synthesis、High Bandwidth Memory、Hardware Acceleration

Low-Voltage Single-Ended Signaling with DECAP Allocation and Phase Coding for 3DICs

電子研究所・共同指導：黃柏蒼

矽穿孔、靜電防護、低電壓擺幅、去耦電容、相位編碼、串擾減少、Through Silicon Via、Electrostatic Discharge、Low Voltage Swing、Decoupling capacitor、Phase Coding、Crosstalk Reduction

Resource Efficient and Low Latency GNN-based Particle Tracking on FPGA

電子研究所・共同指導：賴伯承

大型強子對撞機、圖神經網路加速器、現場可程式化閘陣列、高階合成、Large Hadron Collider、GNNs Accelerator、FPGA、High Level Synthesis

On Generating Cell Library for Commercial FinFET Nodes

電子研究所

標準元件庫、擺置、繞線、自動化、線性規劃、鰭式場效電晶體、standard cell library、placement、routing、automatic、linear programming、FinFET

On Design Constraints Aware Redistribution Layer Routing for Fan-Out Packages

電子研究所

實體電路自動化、重分佈層繞線、扇出封裝、physical design automation、redistribution layer routing、fan-out package

On Generating MAC Layout for Meeting Cap Ratio in In-ReRAM-Computing Architecture

電子研究所

寄生效應、電容匹配、佈局、繞線、乘加電路、parasitic effect、capacitance matching、placement、routing、multiply-and-accumulate circuit

Placement-Driven Die-Level Partitioning on multi-die FPGA

電子研究所

實體化設計、多晶片FPGA、分群、擺放優化、Physical Design、Multi-die FPGA、Partition、Placement-driven

On Efficient Porting Planar Cell Library for Design Migrations in Foundries and Technologies

電子研究所

遷移、單元佈局、標準單元、設計規則、隅角編織法、約束圖、migration、cell layout、standard cell、design rules、corner stitch、constraint graph

On Redefining Routing Strategies and Resources in Modern Package Designs

電子研究所

基板繞線、球柵陣列封裝、細部繞線、Substrate Routing、Ball Grid Array (BGA)、Detailed Routing

Considering Merging Diffusion and Optimizing Pin Locations for Cost and Performance-aware Analog Layout Design

電子研究所・共同指導：林柏宏

類比電路合成、同步佈局與繞線、擴散區合併、擴散區拆分、多引腳決策、序列對、Analog layout synthesis、simultaneous placement and routing、diffusion merge、diffusion split、multiple pin decision、sequence pair

Performance Oriented Automatic Analog Layout Synthesis Methodology

電子研究所・共同指導：劉建男

類比電路佈局自動化、擺置、繞線、佈局遷移、序列對、Analog layout automation、Placement、Routing、Layout migration、Sequence pair

On-Interposer Decoupling Capacitors Placement for Interposer-based 3DIC

電子研究所

三維積體電路、電源供應網路、電源完整性、去耦合電容、電容擺放、模擬退火、3DIC、PDN、Power integrity、Decoupling Capacitor、Decap Placement、Simulated Annealing

A Prototyping Framework for System on Module Replanning

電子研究所・共同指導：江蕙如

靜態電路壓降、實體電路自動化、線性規劃、系統封裝、系統模組、static IR-drop、PCB routing、Board-Package Floorplan、Partition、System on Module、System in Package

On Automating Binary-Weighted Capacitor Layout for Custom SAR ADC

電機工程學系・共同指導：陳信宏

寄生效應、電容匹配、佈局、繞線、中心對稱、類比數位轉換器、線性規劃、parasitic effect、capacitance matching、placement、routing、commoncentroid、analog-to-digital converter、linear programming

Hardening 3DIC Power Distribution Network by Predicting Worse TSV/Bump Faults

電子研究所・共同指導：林柏宏

三維積體電路、電源供應網、矽穿孔、凸塊、壓降、容錯、3DIC、PDN、TSV、Bump、IR-drop、Fault-tolerance

Identifying Congestion Regions for Routability Improvement on Display Driver IC Layout

電子研究所

實體化設計、可繞度、預測繞線壅擠、擺置、自動佈局繞線、Physical design、Routability、Congestion prediction、Placement、APR

A Study on Congestion Refinement for Display Driver IC Layout

電子研究所・共同指導：劉建男

實體設計、顯示器驅動、繞線擁擠、標準元件膨脹、模組擺放調整、Physical Design、Display Driver、Routing Congestion、Cell Inflation、Module Adjustment

Improving the Quality of Physical Unclonable Functions (PUF) on FPGAs

電機資訊國際學程

物理不可仿製功能 (PUF)、環形震盪器 (RO)、現場可程式化邏輯閘陣列 (FPGA)、Physical Unclonable Function (PUF)、Ring Oscillator (RO)、Field Programmable Gate Array (FPGA)

Validating IR-Drop Partial Results via ANN Assistance

電機資訊國際學程

Static IR drop、ANN、Deep learning、APR、PDN、靜態電路壓降、人工神經網路、深度學習、實體設計自動化、電源傳遞網路

On Reducing LDE variations In Modern Analog Placement

電機資訊國際學程・共同指導：林柏宏

模擬佈局、模擬放置、分層b*樹、佈局效應、擴散 區的長度、來源包括井鄰近效應、和氧化物到氧化物間隔效應、Analog layout、analog placement、hierarchical B*-tree (HB*-Tree)、layout dependent effect (LDE)、length of oxide diffusion (LOD)、well proximity effect (WPE)、oxide-to-oxide spacing effect (OSE)

Timing-driven partition on multi-die FPGAs

電子研究所

電路分群、現場可程式化邏輯閘陣列、多晶片現場可程式化邏輯閘陣列、實體電路設計、Partitioning、Field Programmable Gate Array、Multi-die FPGA、Physical Design

Timing Driven Logic Replication on Multi-Die FPGAs

電子研究所

時序優化、邏輯閘、複製、FPGA、Logic replication、multi-die、Timing-Driven

Performance-Driven Analog Layout Synthesis

電機資訊國際學程

類比電路佈局合成、單調電流方向、PCP約束、序列對、代表序列對、局部單調電流方向、主極點、Analog layout synthesis、Monotonic current paths、PCP constraints、Sequence-pair、Representative sequence-pair、Partial-monotonic、Dominant poles

An Irregular Power TSV Placement Algorithm for 3D IC

電子研究所・共同指導：劉建男

矽穿孔、電源完整性、三維積體電路、電壓衰退、TSV、power integrity、3D IC、IR-drop

Power Noise Suppression Design Methodology using Active Decoupling Capacitors for TSV 3DIC

電子研究所・共同指導：黃柏蒼

三維矽穿孔、主動式去耦電容、電源雜訊、TSV 3DIC、Active Decoupling Capacitor、Power Noise

On Generating ASAP7 Cells with MCF and DP-Based Layout Planning

電子研究所

標準元件庫、電子設計自動化、動態規劃擺置、多物網路流繞線、Standard cell library、Electronic design automation、DP-based placement、MCF-based routing

SVM-Based IR Drop Classification for Non-Uniform Power Delivery Network Analysis

電子研究所・共同指導：劉建男

支持向量機、電路壓降、電源供應網路、SVM、support vector machine、IR drop、PDN、power delivery network

Learning Based Placement Refinement to Reduce DRC Short Violations

電子研究所

擺置、機器學習、違反短路、預測、Placement、Machine Learning、Short Violation、Prediction

A Design Flow for Power Stripes and Micro Bumps Planning on Modern Chip-Package Co-Design

電子研究所

微凸塊、電源走線、Micro bump、Power stripe

A Grid-Based Routing Algorithm for Customized Peripheral Circuits of SRAM System

電子研究所

電路佈局、自動化、記憶體系統、網格狀繞線、layout、cell generation、SRAM、routing

Timing Driven Partition on Multi-FPGA System with Predictive TDM Estimation

電子研究所

現場可程式化邏輯閘陣列、分時多工、分群、實體設計、FPGA、Time-Division-Multiplexing、Partitioning、Physical Design

On Pre-Assignment Routing for Irregular Bumps on BGA Packages

電子研究所

實體設計、繞線、IC 封裝、印刷電路板、Physical Design、Routing、IC Package、Printed Circuit Board

A case study of analog layout generations in automatic and manual approaches for 65nm variable gain amplifier.

理學院應用科技學程

類比電路佈局、電子設計自動化、佈局、analog circuit layout、EDA、Placement

Light-Load Efficiency Enhancement in wave tracking control DC-DC Buck Converter

電機學院電子與光電學程・共同指導：陳科宏

固定導通時間控制、虛擬波跟蹤技術、等效串連阻抗、Conventional constant-on-time (COT) control、equivalent series resistance (ESR)、pseudo wave tracking technique、high efficiency wave tracking control buck converter

On Power Supply Pads Planning for Wire-bonded IC

電子研究所

電源墊、電壓降、電源供應網絡、IO pad、IR drop、power delivery network

Extending ML-OARSMT to Net Open Locator with Efficient and Effective Boolean Operations

電子研究所

繞線、實體設計、直角史坦納樹、避障、布林操作、routing、physical design、rectilinear Steiner tree、obstacle-avoidance、Boolean operations

Ultra-fast Performance Exploration of Analog Designs via Learning-based Framework

電子研究所

類比電路、元件參數調整、機器學習、基因演算法、支援向量機、analog、machine learning、device sizing、genetic algorithm、support vector machine

Irregular Bumps Design Planning for Modern Ball Grid Array Packages

電子研究所・共同指導：周景揚

球閘陣列、界面凸塊、Flip-chip、Package、Bump、Ball

A Novel Partition-Based Cell Generation for High Performance and Printability in Advanced Node

電子研究所・共同指導：周景揚

電子設計自動化、一維佈局、以分割為基礎、列印度、高效率、先進製程、EDA、1-D layout、partition-based、printability、Efficiency、Advanced technology

On Clocking and Placement Techniques for Nanometer Designs

電子研究所

實體設計自動化、時鐘樹合成、擺置、低功率、clock tree synthesis、placement、low power、slew、routability

Utilizing Pin Manipulation and Spare Cells to Obfuscate Interconnect Structures in Split Manufacturing

電機工程學系・共同指導：溫宏斌

拆分製造、混淆電路、備用標準單元、硬體安全、Split manufacturing、spare cell、via、hardware security、routing

More Effective Power Network Prototyping by Analytical and Centroid Learning

電子研究所

電源供應網路、電壓降、Power Distribution Network、IR-Drop

On Droplet Routing and Reliability Hardening in Digital Microfluidic Biochips

電子研究所・共同指導：何宗易

數位式微流體晶片、可靠度、液滴繞線、檢查點、實體設計、Digital Microfluidic Biochip、Reliability、Droplet Routing、Checkpoint、Physical design

Power Switch Allocation Aware Re-Floorplanning

電子研究所

省電、佈局、power switch、floorplan

A Learning-Based Methodology for Routability Prediction in Placement

電機工程學系・共同指導：溫宏斌

細部繞線、全域繞線、機器學習、擺置、可繞度、routability、global routing、DRC violations、detailed routing、placement、machine learning

Models and Algorithms for Custom Routing Tasks

電子研究所

實體設計自動化、繞線、演算法、印刷電路板、類比電路佈局原型設計、Physical Design Automation、Routing、Algorithm、Printed Circuit Board、Analog Layout Prototype

Clock-Aware Incremental Packing for Heterogeneous FPGAs

電子研究所

擺置器、叢集、時脈、FPGA、placement、packing

Synthesizing Performance-targeted Analog Layout via Early Subcircuit-level Post-simulation

電子研究所

類比電路自動化、後期模擬、Analog design automation、Post-simulation

An Analytical Placer for Heterogeneous FPGAs via Rough-Placed Packing

電子研究所

實體設計自動化、佈局、叢集、Physical design automation、Placement、Packing

Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization

電子研究所

異質晶片、三維積體電路、電源供應網路、模型化、heterogeneous chip、3DIC、power delivery network、modeling

A Bump/TSV Fault Tolerance Scheme for Power Delivery Networks in 3D IC

電子研究所

三維積體電路、電源供應網路、錯誤容忍、3D ICs、Power Delivery Network、Fault Tolerance

A Data Mining and Density Estimation Based Methodology for Noise Sensor Placement

電子工程學系 電子研究所

電壓雜訊感測器擺置、近臨界電壓計算、電壓真實性、Noise sensor placement、Near threshold computing、Power integrity

Placement Optimization in Cyber-Physical Digital Microfluidic Biochips

電子工程學系 電子研究所

生物晶片、布局、智慧整合感控、感測器、最佳化、biochip、placement、cyber-physical、sensor、optimization

Incremental Placement and Gate Sizing for Leakage Power Reduction

電子工程學系 電子研究所・共同指導：江蕙如

邏輯閘尺寸調整、增量式佈局、拉格朗日鬆弛技術、降低靜態功率消耗、gate sizing、incremental placement、Lagrangian Relaxation、leakage power reduction

A Comparative Study on Multisource Clock Network Synthesis

電子工程學系 電子研究所

時脈分佈網路、混合時脈架構、多源時脈樹合成、時脈網格、不規則網格、分節點決定、clock distribution network、hybrid clock architecture、multisource CTS、clock mesh、non-uniform mesh、tap point determination

Methodologies on Rapid Analog Circuit Synthesis and Layout Migration

電子工程學系 電子研究所

類比積體電路、電子設計自動化、三角化、基因演算法、積體電路先進製程、遷移設計、類比電路合成、對稱性、效能最佳化、效能探索、Analog Circuit、Design Migration、Triangulation、Genetic Algorithm、Constraint、Advanced Technology Node、Analog cirucit synthesis、Performance exploration、Delaunay Triangulation

Design and simulation of USB3 Load board high speed channels

電機學院電子與光電學程

高速通道、訊號完整性、high speed channels、Signal Integrity

A Fast Integrated Placement and Routing Framework for Floorplan Prototyping

電子工程學系 電子研究所

佈局、擺放、繞線、繞線擁擠估計、Floorplan、Placement、Routing、Routing Congestion Estimation

On Optimizing the Performance Metrics and Automating the Migration Process in Analog Layout Synthesis

電子工程學系 電子研究所

性能最佳化、驗證自動化、performance optimization、verification automation

On Efficient Incremental Placement for Timing Improvement

電子工程學系 電子研究所

時態、布局、增量布局、timing、placement、incremental placement

On synthesizing 2.5D IC power delivery network: generation, analysis and optimization

電子工程學系 電子研究所

電源供應網、分群法、電壓降、Power Delivery Network、Clustering Method、IR-Drop

Implementation of reusable analog layout prototyping with planar triangulation on low-voltage low-dropout regulator

電機學院電子與光電學程

類比電路自動化佈局方式、analog layout automation

An ESD aware Floorplan Algorithm with Efficient CDM Estimation for Multiple Power Domain Designs

電子工程學系 電子研究所

靜電放電、帶電器件模型、電源箝位器、模擬、Electrostatic Discharge、Charged Device Model、power clamp、simulation

Quadratic Placement Algorithm Using Gaussian Blurring and Fixed Point Technique

電子工程學系 電子研究所

佈局演算法、Global Placement

Cost-Effective Decoupling Capacitor Selection For Beyond Die Power Integrity

電子工程學系 電子研究所

電源完整性、去耦合電容、Power Integrity、Decoupling Capacitor

TSV and micro-bump co-planning for 3D IC manufacturing yield improvement

電子工程學系 電子研究所

矽穿孔、TSV

Routability-Driven Bump Assignment for Chip-Package Co-Design

電子工程學系 電子研究所

界面凸塊規劃、晶片與封裝共同設計、逃脫繞線、重分配層繞線、封裝繞線、封裝布置規畫、bump assignment、chip-package co-design、escape routing、RDL routing、substrate routing、package planning

An Implementation of Integrated Hierarchical Synthesis in Op-Amp Circuits

平面顯示技術碩士學位學程

類比電路最佳化、自動化電路效能探索、類比電路模擬、整合式電路設計、階層運算放大器設計、階層類比電路設計、optimization、performance evaluation、space exploration、analogue circuits、circuit simulation、integrated circuit design、differential operational amplifier、hierarchical global-to-local search process、integrated hierarchical op-amp circuit synthesis、integrated hierarchical analog circuit synthesis、performance mapping、performance metrics、opamp circuit design、trade-off aspect identification

On Improving Analog Synthesis Efficiency via Agile Genetic Exploration and Stochastic Optimization

電子工程學系 電子研究所・共同指導：江蕙如

類比電路、平行化、基因演算法、階層合成、動態模擬、多目標的問題、非均勻、Analog Circuit、Parallel、Genetic Algorithm、Hierarchical Synthesis、Stochastic Simulation、Multi-objective Problem、Non-uniform

ACER: An Agglomerative Clustering Based Electrode Addressing and Routing Algorithm for Pin-Constrained EWOD Chips

電子工程學系 電子研究所

微流體生物晶片、繞線、EWOD、biochip、routing

On Power Density Mitigation for Thermal Aware Placement Optimization

電子工程學系 電子研究所

熱感知擺放、Thermal Aware Placement

A Dose Map Generator for Ion Implantation

電子工程學系 電子研究所

離子、離子植入、閘止電應、Ion、Implantation、Vth

High Efficiency Multiphase Boost Converter Over a Wide Load Range

電機學院電子與光電學程・共同指導：陳科宏

升壓、轉換器、全載範圍、高效率、Boost、dc dc converter、Wide Load Range、High Efficiency

Simultaneous Escape Routing Considering Length Matching of Differential Pairs

電子工程學系 電子研究所・共同指導：郭建男

差動對、長度匹配、同時跳脫繞線、differential pair、length matching、simultaneous escape routing、PCB routing

On analyzing and Improving ESD protection in Area-I/O Flip-Chip Design

電機學院電子與光電學程

輸出入緩衝器、靜電防護、覆晶式設計、Area-I/O、ESD protection、Flip-Chip Design

Cosynthesis of Clock Tree and Flip-Flop Redistribution

電子工程學系 電子研究所

時脈樹、共同合成、正反器、Clock tree、Cosynthesis、Flip-flop

On Constructing Low Power and Robust Clock Tree

電子工程學系 電子研究所

時鐘樹、低功率、clock tree、low power

Enhanced and Efficient DCT Based Thermal Model Construction and Its Application to Thermal-Aware Placement

電子工程學系 電子研究所

熱感知放置、Thermal Aware Placement

The Algorithms for Chip-Package-Board Interfacing

電子工程學系 電子研究所

電子設計自動化、繞線、重新分佈層、共同設計、EDA、ROUTING、RDL、CODESIGN

On Exploration and Simulation for the Placement of Inter-Stratum Thermal Pad and Thermal Through Silicon Via in 3-D IC

電機學院電子與光電學程

三維積體電路、熱矽穿孔、層間散熱片、熱消散、3D ICs、thermal through silicon via、inter-stratum thermal pad、thermal dissipation