林柏宏

Low-Latency Spatial-Correlation-Enhanced Histogram Peak Detection for SPAD-Based dToF LiDAR

前瞻半導體研究所・共同指導：李鎮宜

單光子雪崩二極體、直接飛行時間、光達、空間相關性、直方圖峰值偵 測、低延遲、single-photon avalanche diode、direct time-of-flight、LiDAR、spatial correlation、histogram peak detection、low latency

Circuit-Topology-Aware Unit-Device Banking for Common-Centroid Placement of FinFET Analog Circuits

智慧與綠能產學研究所

類比佈局、共質心擺置、FinFET、單元元件分組、可繞通率、模擬退火、analog placement、common-centroid placement、unit-device banking、routability、simulated annealing

Automatic Extraction of Component Dimensions from the Package Drawing in Electronic Component Datasheet

智慧與綠能產學研究所

電子元件封裝視圖、規格書圖面理解、尺寸結構重構、幾何語意關聯性分析、尺寸萃取、CAD/EDA 自動化、IC package drawing、datasheet understanding、structured reconstruction、geometricsemantic association、dimension extraction、CAD/EDA automation

LLM-Assisted Over-Current Protection Configuration for Power ICs in PCB Design

前瞻半導體研究所

過電流保護、印刷電路板設計、驗證、Overcurrent Protection、PCB Design、Verification

Voronoi Diagram-based Shielding-aware Power/Ground Plane Generation on Redistribution Layers

前瞻半導體研究所

再分佈層、電源／接地平面生成、具屏蔽感知設計、沃羅諾伊圖、訊號與電源完整性協同設計、受限德勞內三角剖分、Redistribution layers (RDLs)、power/ground (P/G) plane generation、shielding-aware design、Voronoi diagram、signal integrity–power integrity (SI–PI) co-design、constrained Delaunay triangulation (CDT)

Parallel Utility-Guided Multi-Bit Flip-Flop Clustering with Timing and Power Co-Optimization

智慧計算與科技研究所・共同指導：賴伯承

電子設計自動化、實體設計自動化、時序最佳化、多位元正反器、佈局最佳化、Electronic Design Automation、Physical Design Automation、Clock Power Optimization、Multi-Bit Flip-Flop、Placement Optimization

RTL2Route: Predicting Routing Congestion at RTL through High Fidelity Mapping

前瞻半導體研究所

繞線擁塞、暫存器傳輸級、圖神經網路、跨抽象層映射、節點嵌入、GraphSAGE、Routing Congestion、RTL、GNN、Cross-Abstraction Mapping、Node Embedding

Automatic Pin Type Classification Using Abbreviation Expansion in Electronic Component Specifications

智慧系統與應用研究所

電子設計自動化、檢索式增強生成、大型語言模型、腳位類型分類、語意嵌入、Electronic Design Automation、Retrieval-Augmented Generation、Large Language Models、Pin Type Classification、Semantic Embedding

A Weight-Based Multibit Flip-Flop Banking Framework for Configurable Power, Performance, and Area Co-Optimization

電子研究所・共同指導：陳宏明

多位元正反器、MBFF 合併、正反器叢集、動態功耗、Multibit flip-flop、MBFF banking、flip-flop clustering、dynamic power

Multiple-Part Symbol Creation for Schematic Design with Automatic Pin Group Extraction

智慧與綠能產學研究所

原理圖符號生成、多部件元件、引腳群組提取、引腳排序、產業資料集評估、Schematic Symbol Generation、Multiple-Part Symbol、Pin Group Extraction、DBSCAN、Pin Ordering、Industrial Dataset Evaluation

Predict Routing Congestion from RTL Code Stage

智慧系統與應用研究所

繞線擁塞、暫存器傳輸級程式碼、Verilog、圖神經網路、GraphSAGE、擁塞圖、Routing congestion、RTL code、Graph neural network、Congestion map

Placement Refinement and Shielded Routing for Analog Circuit Layouts

電子研究所・共同指導：劉建男

類比電路、佈線、屏蔽約束、Analog Circuit、Routing、Shielding Constraint

Netlistify: Transforming Circuit Schematics into Netlists with Deep Learning

智慧與綠能產學研究所

網表生成器、符號偵測、影像分類、Transformer、Netlist generator、Symbol detection、image classification

Reducing Storage Size in Multi-Bit Retention Registers Considering Both Essential and Redundant Flip-Flops

智慧系統與應用研究所

電源門控、狀態保持、保持鎖存器、保持暫存器、多位元、漏電功耗、power gating、state retention、retention latch、retention register、multi-bit、leakage powers

Accelerating PCB Design by Automated Component Information Extraction from Electronic Component Datasheets

智慧與綠能產學研究所

電子元件規格書、自動化元件資訊提取、關聯性分析、光學字符識別、表格句子轉換、Electronic Component Datasheets、Automated Component Information Extraction、Relationship Analysis、Optical Character Recognition、Table-Sentence Transformation

A Clustering and Fitting Methodology of SoC Performance Monitors Considering Multiple Critical Paths

智慧系統與應用研究所

單晶片系統、環形振盪器、晶片效能監控、system-on-chip(SoC)、ring oscillator(RO)、chip performance monitor(CPM)

Voronoi Diagram-based Multiple Power/Ground Plane Generation on Redistribution Layers in 3D ICs

智慧系統與應用研究所

三維積體電路、實體設計、再分佈層、電源接地平面、沃羅諾伊圖、3D-IC、physical design、redistribution layer(RDL)、power/ground plane、Voronoi diagram

Sweepline-Based Algorithm for Layer Assignment on D2D Package Routing

電子研究所・共同指導：劉建男

2.5D 集成電路、層分配、芯片對芯片封裝佈線、預分層、2.5D IC、layer assignment、die-to-die package routing、pre-layer assignment

Inference PVT Conditions for Standard Cell based on Residual Learning

智慧與綠能產學研究所

標准電路單元庫、標准電路單元庫表徵、殘差學習、PVT條件、推理條件、Standard cell library、Standard cell library characterization、Residual learning、PVT conditions、Inference condition

A Novel SoC Performance Monitoring and Prediction Methodology Considering PVT-to-Delay Sensitivities

智慧系統與應用研究所

單晶片系統、環形振盪器、晶片效能監控、關鍵路徑延遲、延遲敏感性、system-on-chip(SoC)、ring oscillator(RO)、chip performance monitor(CPM)、critical path delay、delay sensitivity

GPU-Accelerated Logic Rewriting for VLSI with High Logic Depth

智慧系統與應用研究所

AND-Inverter圖、邏輯重寫、布林函數、優化、GPU加速、AND-Inverter Graph、Logic Rewriting、Boolean Functions、Optimization、GPU-Accelerating

Converting Schematic Image to Circuit Netlist based on Deep Learning and Symbol Connectivity Association

智慧與綠能產學研究所

網表生成器、導線交叉、符號偵測、方向辨識、特徵附加、引腳關聯、Netlist generator、Wire crossing、Symbol Detection、Orientation recognition、Feature appending、Pin association

Learning and Synthesizing Analog Building Block Layouts with Variational Autoencoders

智慧系統與應用研究所・共同指導：蘇冠暐

類比佈局、子電路佈局、神經網絡、變分自動編碼器、繞線引導、佈局遷移、analog layout、building block layout、layout migration、neural network、variational autoencoder、routing guidance

ANALOG PLACEMENT USING REINFORCEMENT LEARNING WITH GRASPSAGE BASED ON BOUNDED-SLICELINE GRID STRUCTURE

智慧計算與科技研究所

集合電路、佈局、強化學習、有界切片線網格結構、圖採樣和聚合、類比佈局約束、integrated circuit (IC)、placement、reinforcement learning (RL)、bounded-sliceline grid (BSG) structure、Graph SAmple and aggreGatE (GraphSAGE)、analog placement constraint

Automatic Analog Schematic Diagram Generation based on Building Block Classification and Reinforcement Learning

智慧系統與應用研究所

類比電路、電路圖生成、電路圖可視化、電路結構模塊、強化學習、Analog circuit、Schematic generation、Schematic visualization、Building block、Reinforcement learning

A Fast Behavioral Model for ReRAM Crossbar Array to Support the Verification of In-Memory Computing Design

電子研究所・共同指導：劉建男

電阻式記憶體、非理想效應、電阻式記憶體內運算、行為模型、ReRAM、non-ideal effect、in ReRAM computing、behavioral model

SSIOE: Self-Supervised Indoor Occupancy Estimation For Intelligent Building Management

智慧系統與應用研究所・共同指導：黃敬群

占用估計、深度學習方法、環境監測與管理、感測器融合、基於感測器的控制、自監督式學習、元學習、Occupancy Estimation、Deep Learning Methods、Environment Monitoring and Management、Sensor Fusion、Sensor-based Control、Self-Supervised Learning、Meta-Learning

A Novel Machine-Learning based SoC Performance Monitoring Methodology under Wide-Range PVT Variations with Unknown Critical Paths

智慧系統與應用研究所

系統單晶片、製程參數、環形振盪器、晶片效能監控、關鍵路徑延遲、SoC、PVT、ring oscillator、chip performance monitor、critical path delay

Massive Figure Extraction and Classification in Electronic Component Datasheets for Accelerating PCB Design Preparation

智慧系統與應用研究所

印刷電路板、物件偵測、電子元件數據表、電子元件規格、預消化數據、精確融合模型、邊界框細化、printed-circuit-board (PCB)、object detection、electronic component datasheets、electronic component specification-YOLO (ECS-YOLO)、predigesting data、exact fusion model (EFM)、bounding box refinement

Considering Merging Diffusion and Optimizing Pin Locations for Cost and Performance-aware Analog Layout Design

電子研究所・共同指導：陳宏明

類比電路合成、同步佈局與繞線、擴散區合併、擴散區拆分、多引腳決策、序列對、Analog layout synthesis、simultaneous placement and routing、diffusion merge、diffusion split、multiple pin decision、sequence pair

Hardening 3DIC Power Distribution Network by Predicting Worse TSV/Bump Faults

電子研究所・共同指導：陳宏明

三維積體電路、電源供應網、矽穿孔、凸塊、壓降、容錯、3DIC、PDN、TSV、Bump、IR-drop、Fault-tolerance

On Reducing LDE variations In Modern Analog Placement

電機資訊國際學程・共同指導：陳宏明

模擬佈局、模擬放置、分層b*樹、佈局效應、擴散 區的長度、來源包括井鄰近效應、和氧化物到氧化物間隔效應、Analog layout、analog placement、hierarchical B*-tree (HB*-Tree)、layout dependent effect (LDE)、length of oxide diffusion (LOD)、well proximity effect (WPE)、oxide-to-oxide spacing effect (OSE)